source: SVN/rincon/u-boot/board/netstal/hcu5/hcu5.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

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Signed-off-by: Tim Harvey <tharvey@…>

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1/*
2 *(C) Copyright 2005-2008 Netstal Maschinen AG
3 *    Niklaus Giger (Niklaus.Giger@netstal.com)
4 *
5 *    This source code is free software; you can redistribute it
6 *    and/or modify it in source code form under the terms of the GNU
7 *    General Public License as published by the Free Software
8 *    Foundation; either version 2 of the License, or (at your option)
9 *    any later version.
10 *
11 *    This program is distributed in the hope that it will be useful,
12 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *    GNU General Public License for more details.
15 *
16 *    You should have received a copy of the GNU General Public License
17 *    along with this program; if not, write to the Free Software
18 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 */
20
21#include <common.h>
22#include <asm/processor.h>
23#include <ppc440.h>
24#include <asm/io.h>
25#include  "../common/nm.h"
26
27DECLARE_GLOBAL_DATA_PTR;
28
29extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
30
31#undef BOOTSTRAP_OPTION_A_ACTIVE
32
33#define SDR0_CP440              0x0180
34
35#define SYSTEM_RESET            0x30000000
36#define CHIP_RESET              0x20000000
37
38#define SDR0_ECID0              0x0080
39#define SDR0_ECID1              0x0081
40#define SDR0_ECID2              0x0082
41#define SDR0_ECID3              0x0083
42
43#define SYS_IO_ADDRESS                  (CFG_CS_2 + 0x00e00000)
44#define SYS_SLOT_ADDRESS                (CFG_CPLD + 0x00400000)
45#define HCU_DIGITAL_IO_REGISTER (CFG_CPLD + 0x0500000)
46#define HCU_SW_INSTALL_REQUESTED        0x10
47
48/*
49 * This function is run very early, out of flash, and before devices are
50 * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
51 * of being in the init_sequence array.
52 *
53 * The SDRAM has been initialized already -- start.S:start called
54 * init.S:init_sdram early on -- but it is not yet being used for
55 * anything, not even stack. So be careful.
56 */
57
58int board_early_init_f(void)
59{
60
61#ifdef BOOTSTRAP_OPTION_A_ACTIVE
62        /* Booting with Bootstrap Option A
63         * First boot, with CPR0_ICFG_RLI_MASK == 0
64         * no we setup varios boot strapping register,
65         * then we do reset the PPC440 using a chip reset
66         * Unfortunately, we cannot use this option, as Nto1 is not set
67         * with Bootstrap Option A and cannot be changed later on by SW
68         * There are no other possible boostrap options with a 8 bit ROM
69         * See Errata (Version 1.04) CHIP_9
70         */
71
72        u32 cpr0icfg;
73        u32 dbcr;
74
75        mfcpr(CPR0_ICFG, cpr0icfg);
76        if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
77                mtcpr(CPR0_MALD,   0x02000000);
78                mtcpr(CPR0_OPBD,   0x02000000);
79                mtcpr(CPR0_PERD,   0x05000000);  /* 1:5 */
80                mtcpr(CPR0_PLLC,   0x40000238);
81                mtcpr(CPR0_PLLD,   0x01010414);
82                mtcpr(CPR0_PRIMAD, 0x01000000);
83                mtcpr(CPR0_PRIMBD, 0x01000000);
84                mtcpr(CPR0_SPCID,  0x03000000);
85                mtsdr(SDR0_PFC0,   0x00003E00);  /* [CTE] = 0 */
86                mtsdr(SDR0_CP440,  0x0EAAEA02);  /* [Nto1] = 1*/
87                mtcpr(CPR0_ICFG,   cpr0icfg | CPR0_ICFG_RLI_MASK);
88
89                /*
90                 * Initiate system reset in debug control register DBCR
91                 */
92                dbcr = mfspr(dbcr0);
93                mtspr(dbcr0, dbcr | CHIP_RESET);
94        }
95        mtsdr(SDR0_CP440, 0x0EAAEA02);  /* [Nto1] = 1*/
96#endif
97        mtdcr(ebccfga, xbcfg);
98        mtdcr(ebccfgd, 0xb8400000);
99
100        /*
101         * Setup the GPIO pins
102         */
103        out32(GPIO0_OR, 0x00000000);
104        out32(GPIO0_TCR, 0x7C2FF1CF);
105        out32(GPIO0_OSRL, 0x40055000);
106        out32(GPIO0_OSRH, 0x00000000);
107        out32(GPIO0_TSRL, 0x40055000);
108        out32(GPIO0_TSRH, 0x00000400);
109        out32(GPIO0_ISR1L, 0x40000000);
110        out32(GPIO0_ISR1H, 0x00000000);
111        out32(GPIO0_ISR2L, 0x00000000);
112        out32(GPIO0_ISR2H, 0x00000000);
113        out32(GPIO0_ISR3L, 0x00000000);
114        out32(GPIO0_ISR3H, 0x00000000);
115
116        out32(GPIO1_OR, 0x00000000);
117        out32(GPIO1_TCR, 0xC6007FFF);
118        out32(GPIO1_OSRL, 0x00140000);
119        out32(GPIO1_OSRH, 0x00000000);
120        out32(GPIO1_TSRL, 0x00000000);
121        out32(GPIO1_TSRH, 0x00000000);
122        out32(GPIO1_ISR1L, 0x05415555);
123        out32(GPIO1_ISR1H, 0x40000000);
124        out32(GPIO1_ISR2L, 0x00000000);
125        out32(GPIO1_ISR2H, 0x00000000);
126        out32(GPIO1_ISR3L, 0x00000000);
127        out32(GPIO1_ISR3H, 0x00000000);
128
129        /*
130         * Setup the interrupt controller polarities, triggers, etc.
131         */
132        mtdcr(uic0sr, 0xffffffff);      /* clear all */
133        mtdcr(uic0er, 0x00000000);      /* disable all */
134        mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
135        mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
136        mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
137        mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
138        mtdcr(uic0sr, 0xffffffff);      /* clear all */
139
140        mtdcr(uic1sr, 0xffffffff);      /* clear all */
141        mtdcr(uic1er, 0x00000000);      /* disable all */
142        mtdcr(uic1cr, 0x00000000);      /* all non-critical */
143        mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
144        mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
145        mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
146        mtdcr(uic1sr, 0xffffffff);      /* clear all */
147
148        mtdcr(uic2sr, 0xffffffff);      /* clear all */
149        mtdcr(uic2er, 0x00000000);      /* disable all */
150        mtdcr(uic2cr, 0x00000000);      /* all non-critical */
151        mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
152        mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
153        mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
154        mtdcr(uic2sr, 0xffffffff);      /* clear all */
155        mtsdr(sdr_pfc0, 0x00003E00);    /* Pin function:  */
156        mtsdr(sdr_pfc1, 0x00848000);    /* Pin function: UART0 has 4 pins */
157
158        /* setup BOOT FLASH */
159        mtsdr(SDR0_CUST0, 0xC0082350);
160
161        return 0;
162}
163
164#ifdef CONFIG_BOARD_PRE_INIT
165int board_pre_init(void)
166{
167        return board_early_init_f();
168}
169
170#endif
171
172int sys_install_requested(void)
173{
174        u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
175        return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
176}
177
178int checkboard(void)
179{
180        u16 *hwVersReg    = (u16 *) HCU_HW_VERSION_REGISTER;
181        u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
182        u16 generation = in_be16(boardVersReg) & 0xf0;
183        u16 index      = in_be16(boardVersReg) & 0x0f;
184        u32 ecid0, ecid1, ecid2, ecid3;
185
186        nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
187        mfsdr(SDR0_ECID0, ecid0);
188        mfsdr(SDR0_ECID1, ecid1);
189        mfsdr(SDR0_ECID2, ecid2);
190        mfsdr(SDR0_ECID3, ecid3);
191
192        printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
193
194        return 0;
195}
196
197u32 hcu_led_get(void)
198{
199        return in16(SYS_IO_ADDRESS) & 0x3f;
200}
201
202/*
203 * hcu_led_set  value to be placed into the LEDs (max 6 bit)
204 */
205void hcu_led_set(u32 value)
206{
207        out16(SYS_IO_ADDRESS, value);
208}
209
210/*
211 * get_serial_number
212 */
213u32 get_serial_number(void)
214{
215        u32 *serial = (u32 *)CFG_FLASH_BASE;
216
217        if (in_be32(serial) == 0xffffffff)
218                return 0;
219
220        return in_be32(serial);
221}
222
223
224/*
225 * hcu_get_slot
226 */
227u32 hcu_get_slot(void)
228{
229        u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
230        return in_be16(slot) & 0x7f;
231}
232
233
234/*
235 * misc_init_r.
236 */
237int misc_init_r(void)
238{
239        unsigned long usb2d0cr = 0;
240        unsigned long usb2phy0cr, usb2h0cr = 0;
241        unsigned long sdr0_pfc1;
242
243#ifdef CONFIG_ENV_IS_IN_FLASH
244        /* Monitor protection ON by default */
245        (void)flash_protect(FLAG_PROTECT_SET,
246                            -CFG_MONITOR_LEN,
247                            0xffffffff,
248                            &flash_info[0]);
249
250#ifdef CONFIG_ENV_ADDR_REDUND
251        /* Env protection ON by default */
252        (void)flash_protect(FLAG_PROTECT_SET,
253                            CONFIG_ENV_ADDR_REDUND,
254                            CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
255                            &flash_info[0]);
256#endif
257#endif
258
259        /*
260         * USB stuff...
261         */
262
263        /* SDR Setting */
264        mfsdr(SDR0_PFC1, sdr0_pfc1);
265        mfsdr(SDR0_USB2D0CR, usb2d0cr);
266        mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
267        mfsdr(SDR0_USB2H0CR, usb2h0cr);
268
269        usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
270        usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
271        usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
272        usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;    /*1*/
273        usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
274        usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
275        usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
276        usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
277        usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
278        usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
279
280        /* An 8-bit/60MHz interface is the only possible alternative
281         *  when connecting the Device to the PHY
282         */
283        usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
284        usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;        /*1*/
285
286        /* To enable the USB 2.0 Device function through the UTMI interface */
287        usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
288        usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;          /*1*/
289
290        sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
291        sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;                /*0*/
292
293        mtsdr(SDR0_PFC1, sdr0_pfc1);
294        mtsdr(SDR0_USB2D0CR, usb2d0cr);
295        mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
296        mtsdr(SDR0_USB2H0CR, usb2h0cr);
297
298        /*clear resets*/
299        udelay(1000);
300        mtsdr(SDR0_SRST1, 0x00000000);
301        udelay(1000);
302        mtsdr(SDR0_SRST0, 0x00000000);
303        printf("USB:   Host(int phy) Device(ext phy)\n");
304
305        common_misc_init_r();
306        set_params_for_sw_install( sys_install_requested(), "hcu5" );
307        /* We cannot easily enable trace before, as there are other
308         * routines messing around with sdr0_pfc1. And I do not need it.
309         */
310        if (mfspr(dbcr0) & 0x80000000) {
311                /* External debugger alive
312                 * enable trace facilty for Lauterbach
313                 * CCR0[DTB]=0          Enable broadcast of trace information
314                 * SDR0_PFC0[TRE]       Trace signals are enabled instead of
315                 *                      GPIO49-63
316                 */
317                mtspr(ccr0, mfspr(ccr0)  &~ (CCR0_DTB));
318                mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
319        }
320        return 0;
321}
322#ifdef CONFIG_PCI
323int board_with_pci(void)
324{
325        u32 reg;
326
327        mfsdr(sdr_pci0, reg);
328        return (reg & SDR0_XCR_PAE_MASK);
329}
330
331/*
332 *  pci_pre_init
333 *
334 *  This routine is called just prior to registering the hose and gives
335 *  the board the opportunity to check things. Returning a value of zero
336 *  indicates that things are bad & PCI initialization should be aborted.
337 *
338 *      Different boards may wish to customize the pci controller structure
339 *      (add regions, override default access routines, etc) or perform
340 *      certain pre-initialization actions.
341 *
342 */
343int pci_pre_init(struct pci_controller *hose)
344{
345        unsigned long addr;
346
347        if (!board_with_pci()) { return 0; }
348
349        /*
350         * Set priority for all PLB3 devices to 0.
351         * Set PLB3 arbiter to fair mode.
352         */
353        mfsdr(sdr_amp1, addr);
354        mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
355        addr = mfdcr(plb3_acr);
356        mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
357
358        /*
359         * Set priority for all PLB4 devices to 0.
360         */
361        mfsdr(sdr_amp0, addr);
362        mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
363        addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
364        mtdcr(plb4_acr, addr);  /* Sequoia */
365
366        /*
367         * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
368         * Workaround: Disable write pipelining to DDR SDRAM by setting
369         * PLB0_ACR[WRP] = 0.
370         */
371        mtdcr(plb0_acr, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
372
373        /* Segment1 */
374        mtdcr(plb1_acr, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
375
376        return board_with_pci();
377}
378
379/*
380 *  pci_target_init
381 *
382 *      The bootstrap configuration provides default settings for the pci
383 *      inbound map (PIM). But the bootstrap config choices are limited and
384 *      may not be sufficient for a given board.
385 *
386 */
387void pci_target_init(struct pci_controller *hose)
388{
389        if (!board_with_pci()) { return; }
390        /*
391         * Set up Direct MMIO registers
392         *
393         * PowerPC440EPX PCI Master configuration.
394         * Map one 1Gig range of PLB/processor addresses to PCI memory space.
395         *   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
396         *                0xA0000000-0xDFFFFFFF
397         *   Use byte reversed out routines to handle endianess.
398         * Make this region non-prefetchable.
399         */
400        /* PMM0 Mask/Attribute - disabled b4 setting */
401        out32r(PCIX0_PMM0MA, 0x00000000);
402        out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
403        /* PMM0 PCI Low Address */
404        out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
405        out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
406        /* 512M + No prefetching, and enable region */
407        out32r(PCIX0_PMM0MA, 0xE0000001);
408
409        /* PMM0 Mask/Attribute - disabled b4 setting */
410        out32r(PCIX0_PMM1MA, 0x00000000);
411        out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
412        /* PMM0 PCI Low Address */
413        out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
414        out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
415        /* 512M + No prefetching, and enable region */
416        out32r(PCIX0_PMM1MA, 0xE0000001);
417
418        out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
419        out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
420        out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
421        out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
422
423        /*
424         * Set up Configuration registers
425         */
426
427        /* Program the board's subsystem id/vendor id */
428        pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
429                              CFG_PCI_SUBSYS_VENDORID);
430        pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
431
432        /* Configure command register as bus master */
433        pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
434
435        /* 240nS PCI clock */
436        pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
437
438        /* No error reporting */
439        pci_write_config_word(0, PCI_ERREN, 0);
440
441        pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
442}
443
444/*
445 *  pci_master_init
446 *
447 */
448void pci_master_init(struct pci_controller *hose)
449{
450        unsigned short temp_short;
451        if (!board_with_pci()) { return; }
452
453        /*---------------------------------------------------------------
454         * Write the PowerPC440 EP PCI Configuration regs.
455         *   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
456         *   Enable PowerPC440 EP to act as a PCI memory target (PTM).
457         *--------------------------------------------------------------*/
458        pci_read_config_word(0, PCI_COMMAND, &temp_short);
459        pci_write_config_word(0, PCI_COMMAND,
460                              temp_short | PCI_COMMAND_MASTER |
461                              PCI_COMMAND_MEMORY);
462}
463
464/*
465 *  is_pci_host
466 *
467 *      This routine is called to determine if a pci scan should be
468 *      performed. With various hardware environments (especially cPCI and
469 *      PPMC) it's insufficient to depend on the state of the arbiter enable
470 *      bit in the strap register, or generic host/adapter assumptions.
471 *
472 *      Rather than hard-code a bad assumption in the general 440 code, the
473 *      440 pci code requires the board to decide at runtime.
474 *
475 *      Return 0 for adapter mode, non-zero for host (monarch) mode.
476 *
477 */
478int is_pci_host(struct pci_controller *hose)
479{
480        return 1;
481}
482#endif   /* defined(CONFIG_PCI) */
483
484#if defined(CONFIG_POST)
485/*
486 * Returns 1 if keys pressed to start the power-on long-running tests
487 * Called from board_init_f().
488 */
489int post_hotkeys_pressed(void)
490{
491        return 0;       /* No hotkeys supported */
492}
493#endif /* CONFIG_POST */
494
495#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
496void ft_board_setup(void *blob, bd_t *bd)
497{
498        ft_cpu_setup(blob, bd);
499
500}
501#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
502
503/*
504 * Hardcoded flash setup:
505 * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
506 */
507ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
508{
509        if (banknum == 0) {     /* non-CFI boot flash */
510                info->portwidth = 1;
511                info->chipwidth = 1;
512                info->interface = FLASH_CFI_X8;
513                return 1;
514        } else
515                return 0;
516}
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