source: SVN/rincon/u-boot/board/ns9750dev/lowlevel_init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 7.5 KB
Line 
1/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2003
5 * Texas Instruments, <www.ti.com>
6 * Kshitij Gupta <Kshitij@ti.com>
7 *
8 * Modified for the NS9750 DevBoard by
9 * (C) Copyright 2004 by FS Forth-Systeme GmbH.
10 * Markus Pietrek <mpietrek@fsforth.de>
11 * @References: [1] NS9750 Hardware Reference/December 2003
12 *              [2] ns9750_a.cmd from MAJIC configuration
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33#include <config.h>
34#include <version.h>
35
36#if defined(CONFIG_NS9750DEV)
37# ifndef CONFIG_SKIP_LOWLEVEL_INIT
38#  include <./ns9750_sys.h>
39#  include <./ns9750_mem.h>
40# endif
41#endif
42
43/***********************************************************************
44 * @Function: write_register_block
45 * @Return: nothing
46 * @Descr: Copies the register block of register_offset:register value to
47 *         the registers at base r0. The block is assumed to start in RAM at r1
48 *         and end at r2. The linked RAM base address of U-Boot is assumed to be
49 *         in r5 while the ROM base address we are running from is r6
50 *         Uses r3 and r4 as tempory registers
51 ***********************************************************************/
52
53.macro  write_register_block
54        @@ map the addresses to high memory
55        sub     r1, r1, r5
56        add     r1, r1, r6
57        sub     r2, r2, r5
58        add     r2, r2, r6
59
60        @@ copy all
611:
62        @@ Write register/value pair starting at [r1] to register base r0
63        ldr     r3, [r1], #4
64        ldr     r4, [r1], #4
65        str     r4, [r0,r3]
66        cmp     r1, r2
67        blt     1b
68.endm
69
70_TEXT_BASE:
71        .word   TEXT_BASE       @ sdram load addr from config.mk
72_PHYS_FLASH:
73        .word   PHYS_FLASH_1    @ real flash address (without mirroring)
74_CAS_LATENCY:
75        .word   0x00022000      @ for CAS2 latency
76
77#ifndef CONFIG_SKIP_LOWLEVEL_INIT
78.globl lowlevel_init
79lowlevel_init:
80
81        /* U-Boot may be linked to RAM at 0x780000. But this code will run in
82           flash from 0x0. But in order to enable RAM we have to disable the
83           mirror bit, therefore we have to jump to our real flash address
84           beginning at PHYS_FLASH_1 (CS4 Base). Therefore,
85           _run_at_real_flash_address may be 0x500003b0 while be linked to
86           0x7803b0. So we must modify our linked addresses */
87
88        @@ branch to high memory address, away from 0x0
89        ldr     r5, _TEXT_BASE
90        ldr     r6, _PHYS_FLASH
91        ldr     r0, =_run_at_real_flash_address
92        sub     r0, r0, r5
93        add     r0, r0, r6
94        mov     pc, r0
95        nop                     @ for pipelining
96
97_run_at_real_flash_address:
98        @@ now we are running > PHYS_FLASH_1, safe to enable memory controller
99
100        @@ Write Memory Configuration Registers
101
102        ldr     r0, _NS9750_MEM_MODULE_BASE
103        ldr     r1, =_MEM_CONFIG_START
104        ldr     r2, =_MEM_CONFIG_END
105
106        write_register_block
107
108        @@ Give SDRAM some time to settle
109        @@ @TODO. According to [2] it should be 2 AHB cycles. Check
110
111        ldr     r1, =0x50
112_sdram_settle:
113        subs    r1, r1, #1
114        bne     _sdram_settle
115
116_enable_mappings:
117        @@ Enable SDRAM Mode
118
119        ldr     r1, =_MEM_MODE_START
120        ldr     r2, =_MEM_MODE_END
121
122        write_register_block
123
124        ldr     r3, _CAS_LATENCY @ perform one read from SDRAM
125        ldr     r3, [r3]
126
127        @@ Enable SDRAM and memory mappings
128
129        ldr     r1, =_MEM_ENABLE_START
130        ldr     r2, =_MEM_ENABLE_END
131
132        write_register_block
133
134        @@ Activate AHB monitor
135
136        ldr     r0, =NS9750_SYS_MODULE_BASE
137        ldr     r1, =_AHB_MONITOR_START
138        ldr     r2, =_AHB_MONITOR_END
139
140        write_register_block
141_relocate_lr:
142        /* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to
143           PHYS_FLASH. */
144        mov     r1, ip
145        add     r1, r1, r6
146        mov     ip, r1
147
148        mov     r1, lr
149        add     r1, r1, r6
150        mov     lr, r1
151
152        @@ back to arch calling code
153        mov     pc,     lr
154
155        .ltorg
156
157_NS9750_MEM_MODULE_BASE:
158        .word   NS9750_MEM_MODULE_BASE
159
160_MEM_CONFIG_START:
161        /* Table of 2 32bit entries. First word is register address offset
162           relative to NS9750_MEM_MODULE_BASE, second one is value. They are
163           written in order of appearance */
164
165        @@ Register values taken from [2]
166        .word   NS9750_MEM_CTRL
167        .word   NS9750_MEM_CTRL_E
168
169        .word   NS9750_MEM_DYN_REFRESH
170        .word   (0x6 & NS9750_MEM_DYN_REFRESH_MA)
171
172        .word   NS9750_MEM_DYN_READ_CFG
173        .word   (0x1 & NS9750_MEM_DYN_READ_CFG_MA)
174
175        .word   NS9750_MEM_DYN_TRP
176        .word   (0x1 & NS9750_MEM_DYN_TRP_MA)
177
178        .word   NS9750_MEM_DYN_TRAS
179        .word   (0x4 & NS9750_MEM_DYN_TRAS_MA)
180
181        .word   NS9750_MEM_DYN_TAPR
182        .word   (0x1 & NS9750_MEM_DYN_TRAS_MA)
183
184        .word   NS9750_MEM_DYN_TDAL
185        .word   (0x5 & NS9750_MEM_DYN_TDAL_MA)
186
187        .word   NS9750_MEM_DYN_TWR
188        .word   (0x1 & NS9750_MEM_DYN_TWR_MA)
189
190        .word   NS9750_MEM_DYN_TRC
191        .word   (0x6 & NS9750_MEM_DYN_TRC_MA)
192
193        .word   NS9750_MEM_DYN_TRFC
194        .word   (0x6 & NS9750_MEM_DYN_TRFC_MA)
195
196        .word   NS9750_MEM_DYN_TRRD
197        .word   (0x1 & NS9750_MEM_DYN_TRRD_MA)
198
199        .word   NS9750_MEM_DYN_TMRD
200        .word   (0x1 & NS9750_MEM_DYN_TMRD_MA)
201
202        @@ CS 4
203        .word   NS9750_MEM_DYN_CFG(0)
204        .word   (NS9750_MEM_DYN_CFG_AM | \
205                 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
206
207        .word   NS9750_MEM_DYN_RAS_CAS(0)
208        .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
209                 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
210
211        @@ CS 5
212        .word   NS9750_MEM_DYN_CFG(1)
213        .word   (NS9750_MEM_DYN_CFG_AM | \
214                 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
215
216        .word   NS9750_MEM_DYN_RAS_CAS(1)
217        .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
218                 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
219
220        @@ CS 6
221        .word   NS9750_MEM_DYN_CFG(2)
222        .word   (NS9750_MEM_DYN_CFG_AM | \
223                 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
224
225        .word   NS9750_MEM_DYN_RAS_CAS(2)
226        .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
227                 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
228
229        @@ CS 7
230        .word   NS9750_MEM_DYN_CFG(3)
231        .word   (NS9750_MEM_DYN_CFG_AM | \
232                 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
233
234        .word   NS9750_MEM_DYN_RAS_CAS(3)
235        .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
236                 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
237
238        .word   NS9750_MEM_DYN_CTRL
239        .word   (NS9750_MEM_DYN_CTRL_I_PALL | \
240                 NS9750_MEM_DYN_CTRL_SR | \
241                 NS9750_MEM_DYN_CTRL_CE )
242
243        .word   NS9750_MEM_DYN_REFRESH
244        .word   (0x1 & NS9750_MEM_DYN_REFRESH_MA)
245        @@ No further register settings after refresh
246_MEM_CONFIG_END:
247
248_MEM_MODE_START:
249        .word   NS9750_MEM_DYN_REFRESH
250        .word   (0x30 & NS9750_MEM_DYN_REFRESH_MA)
251
252        .word   NS9750_MEM_DYN_CTRL
253        .word   (NS9750_MEM_DYN_CTRL_I_MODE | \
254                 NS9750_MEM_DYN_CTRL_SR | \
255                 NS9750_MEM_DYN_CTRL_CE )
256_MEM_MODE_END:
257
258_MEM_ENABLE_START:
259        .word   NS9750_MEM_DYN_CTRL
260        .word   (NS9750_MEM_DYN_CTRL_I_NORMAL | \
261                 NS9750_MEM_DYN_CTRL_SR | \
262                 NS9750_MEM_DYN_CTRL_CE )
263
264        @@ CS 4
265        .word   NS9750_MEM_DYN_CFG(0)
266        .word   (NS9750_MEM_DYN_CFG_BDMC | \
267                 NS9750_MEM_DYN_CFG_AM | \
268                 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
269
270        @@ CS 5
271        .word   NS9750_MEM_DYN_CFG(1)
272        .word   (NS9750_MEM_DYN_CFG_BDMC | \
273                 NS9750_MEM_DYN_CFG_AM | \
274                 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
275
276        @@ CS 6
277        .word   NS9750_MEM_DYN_CFG(2)
278        .word   (NS9750_MEM_DYN_CFG_BDMC | \
279                 NS9750_MEM_DYN_CFG_AM | \
280                 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
281
282        @@ CS 7
283        .word   NS9750_MEM_DYN_CFG(3)
284        .word   (NS9750_MEM_DYN_CFG_BDMC | \
285                 NS9750_MEM_DYN_CFG_AM | \
286                 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
287_MEM_ENABLE_END:
288
289_AHB_MONITOR_START:
290        .word   NS9750_SYS_AHB_TIMEOUT
291        .word   0x01000100      @ @TODO not calculated yet
292
293        .word   NS9750_SYS_AHB_MON
294        .word   (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \
295                 NS9750_SYS_AHB_MON_BATC_GEN_IRQ)
296_AHB_MONITOR_END:
297
298#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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