1 | /* |
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2 | * Board specific setup info |
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3 | * |
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4 | * (C) Copyright 2003 |
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5 | * Texas Instruments, <www.ti.com> |
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6 | * |
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7 | * -- Some bits of code used from rrload's head_OMAP1510.s -- |
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8 | * Copyright (C) 2002 RidgeRun, Inc. |
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9 | * |
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10 | * See file CREDITS for list of people who contributed to this |
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11 | * project. |
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12 | * |
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13 | * This program is free software; you can redistribute it and/or |
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14 | * modify it under the terms of the GNU General Public License as |
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15 | * published by the Free Software Foundation; either version 2 of |
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16 | * the License, or (at your option) any later version. |
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17 | * |
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18 | * This program is distributed in the hope that it will be useful, |
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19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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21 | * GNU General Public License for more details. |
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22 | * |
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23 | * You should have received a copy of the GNU General Public License |
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24 | * along with this program; if not, write to the Free Software |
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25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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26 | * MA 02111-1307 USA |
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27 | */ |
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28 | |
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29 | #include <config.h> |
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30 | #include <version.h> |
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31 | |
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32 | #if defined(CONFIG_OMAP1510) |
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33 | #include <./configs/omap1510.h> |
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34 | #endif |
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35 | |
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36 | #define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK)) |
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37 | |
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38 | |
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39 | _TEXT_BASE: |
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40 | .word TEXT_BASE /* sdram load addr from config.mk */ |
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41 | |
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42 | .globl lowlevel_init |
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43 | lowlevel_init: |
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44 | |
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45 | /* |
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46 | * Configure 1510 pins functions to match our board. |
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47 | */ |
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48 | ldr r0, REG_PULL_DWN_CTRL_0 |
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49 | ldr r1, VAL_PULL_DWN_CTRL_0 |
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50 | str r1, [r0] |
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51 | ldr r0, REG_PULL_DWN_CTRL_1 |
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52 | ldr r1, VAL_PULL_DWN_CTRL_1 |
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53 | str r1, [r0] |
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54 | ldr r0, REG_PULL_DWN_CTRL_2 |
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55 | ldr r1, VAL_PULL_DWN_CTRL_2 |
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56 | str r1, [r0] |
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57 | ldr r0, REG_PULL_DWN_CTRL_3 |
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58 | ldr r1, VAL_PULL_DWN_CTRL_3 |
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59 | str r1, [r0] |
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60 | ldr r0, REG_FUNC_MUX_CTRL_4 |
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61 | ldr r1, VAL_FUNC_MUX_CTRL_4 |
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62 | str r1, [r0] |
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63 | ldr r0, REG_FUNC_MUX_CTRL_5 |
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64 | ldr r1, VAL_FUNC_MUX_CTRL_5 |
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65 | str r1, [r0] |
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66 | ldr r0, REG_FUNC_MUX_CTRL_6 |
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67 | ldr r1, VAL_FUNC_MUX_CTRL_6 |
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68 | str r1, [r0] |
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69 | ldr r0, REG_FUNC_MUX_CTRL_7 |
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70 | ldr r1, VAL_FUNC_MUX_CTRL_7 |
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71 | str r1, [r0] |
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72 | ldr r0, REG_FUNC_MUX_CTRL_8 |
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73 | ldr r1, VAL_FUNC_MUX_CTRL_8 |
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74 | str r1, [r0] |
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75 | ldr r0, REG_FUNC_MUX_CTRL_9 |
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76 | ldr r1, VAL_FUNC_MUX_CTRL_9 |
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77 | str r1, [r0] |
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78 | ldr r0, REG_FUNC_MUX_CTRL_A |
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79 | ldr r1, VAL_FUNC_MUX_CTRL_A |
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80 | str r1, [r0] |
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81 | ldr r0, REG_FUNC_MUX_CTRL_B |
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82 | ldr r1, VAL_FUNC_MUX_CTRL_B |
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83 | str r1, [r0] |
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84 | ldr r0, REG_FUNC_MUX_CTRL_C |
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85 | ldr r1, VAL_FUNC_MUX_CTRL_C |
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86 | str r1, [r0] |
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87 | ldr r0, REG_FUNC_MUX_CTRL_D |
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88 | ldr r1, VAL_FUNC_MUX_CTRL_D |
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89 | str r1, [r0] |
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90 | ldr r0, REG_VOLTAGE_CTRL_0 |
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91 | ldr r1, VAL_VOLTAGE_CTRL_0 |
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92 | str r1, [r0] |
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93 | ldr r0, REG_TEST_DBG_CTRL_0 |
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94 | ldr r1, VAL_TEST_DBG_CTRL_0 |
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95 | str r1, [r0] |
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96 | ldr r0, REG_MOD_CONF_CTRL_0 |
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97 | ldr r1, VAL_MOD_CONF_CTRL_0 |
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98 | str r1, [r0] |
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99 | |
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100 | /* Move to 1510 mode */ |
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101 | ldr r0, REG_COMP_MODE_CTRL_0 |
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102 | ldr r1, VAL_COMP_MODE_CTRL_0 |
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103 | str r1, [r0] |
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104 | |
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105 | /* Set up Traffic Ctlr*/ |
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106 | ldr r0, REG_TC_IMIF_PRIO |
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107 | mov r1, #0x0 |
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108 | str r1, [r0] |
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109 | ldr r0, REG_TC_EMIFS_PRIO |
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110 | str r1, [r0] |
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111 | ldr r0, REG_TC_EMIFF_PRIO |
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112 | str r1, [r0] |
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113 | |
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114 | ldr r0, REG_TC_EMIFS_CONFIG |
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115 | ldr r1, [r0] |
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116 | bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */ |
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117 | bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */ |
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118 | str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */ |
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119 | |
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120 | /* Setup some clock domains */ |
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121 | ldr r1, =OMAP1510_CLKS |
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122 | ldr r0, REG_ARM_IDLECT2 |
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123 | strh r1, [r0] /* CLKM, Clock domain control. */ |
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124 | |
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125 | mov r1, #0x01 /* PER_EN bit */ |
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126 | ldr r0, REG_ARM_RSTCT2 |
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127 | strh r1, [r0] /* CLKM; Peripheral reset. */ |
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128 | |
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129 | /* Set CLKM to Sync-Scalable */ |
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130 | /* I supposidly need to enable the dsp clock before switching */ |
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131 | mov r1, #0x1000 |
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132 | ldr r0, REG_ARM_SYSST |
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133 | strh r1, [r0] |
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134 | mov r0, #0x400 |
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135 | 1: |
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136 | subs r0, r0, #0x1 /* wait for any bubbles to finish */ |
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137 | bne 1b |
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138 | |
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139 | ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */ |
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140 | ldr r0, REG_ARM_CKCTL |
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141 | strh r1, [r0] |
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142 | |
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143 | /* setup DPLL 1 */ |
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144 | ldr r1, VAL_DPLL1_CTL |
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145 | ldr r0, REG_DPLL1_CTL |
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146 | strh r1, [r0] |
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147 | ands r1, r1, #0x10 /* Check if PLL is enabled. */ |
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148 | beq lock_end /* Do not look for lock if BYPASS selected */ |
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149 | 2: |
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150 | ldrh r1, [r0] |
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151 | ands r1, r1, #0x01 /* Check the LOCK bit. */ |
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152 | beq 2b /* ...loop until bit goes hi. */ |
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153 | lock_end: |
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154 | |
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155 | /* Set memory timings corresponding to the new clock speed */ |
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156 | |
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157 | /* Check execution location to determine current execution location |
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158 | * and branch to appropriate initialization code. |
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159 | */ |
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160 | mov r0, #0x10000000 /* Load physical SDRAM base. */ |
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161 | mov r1, pc /* Get current execution location. */ |
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162 | /* Zero all but top 6 bits of PC, as they alone detect whether an |
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163 | * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized |
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164 | * valid range for SDRAM on the OMAP 1510/5910. |
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165 | */ |
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166 | and r1, r1, #0xfc000000 |
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167 | cmp r1, r0 /* Compare. */ |
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168 | beq skip_sdram /* Skip over EMIF-fast initialization |
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169 | * if running from SDRAM. |
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170 | */ |
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171 | |
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172 | /* |
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173 | * Delay for SDRAM initialization. |
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174 | */ |
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175 | mov r3, #0x1800 /* value should be checked */ |
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176 | 3: |
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177 | subs r3, r3, #0x1 /* Decrement count */ |
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178 | bne 3b |
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179 | |
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180 | /* |
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181 | * Set SDRAM control values. Disable refresh before MRS command. |
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182 | */ |
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183 | ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */ |
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184 | bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */ |
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185 | orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */ |
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186 | orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */ |
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187 | ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
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188 | str r3, [r2] /* Store the passed value with AR disabled. */ |
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189 | |
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190 | ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */ |
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191 | ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */ |
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192 | str r1, [r2] /* Store the passed value.*/ |
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193 | |
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194 | ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
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195 | str r0, [r2] /* Store the passed value. */ |
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196 | |
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197 | /* |
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198 | * Delay for SDRAM initialization. |
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199 | */ |
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200 | mov r3, #0x1800 |
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201 | 4: |
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202 | subs r3, r3, #1 /* Decrement count. */ |
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203 | bne 4b |
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204 | |
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205 | skip_sdram: |
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206 | |
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207 | /* slow interface */ |
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208 | ldr r1, VAL_TC_EMIFS_CS0_CONFIG |
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209 | ldr r0, REG_TC_EMIFS_CS0_CONFIG |
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210 | str r1, [r0] /* Chip Select 0 */ |
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211 | ldr r1, VAL_TC_EMIFS_CS1_CONFIG |
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212 | ldr r0, REG_TC_EMIFS_CS1_CONFIG |
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213 | str r1, [r0] /* Chip Select 1 */ |
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214 | ldr r1, VAL_TC_EMIFS_CS2_CONFIG |
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215 | ldr r0, REG_TC_EMIFS_CS2_CONFIG |
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216 | str r1, [r0] /* Chip Select 2 */ |
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217 | ldr r1, VAL_TC_EMIFS_CS3_CONFIG |
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218 | ldr r0, REG_TC_EMIFS_CS3_CONFIG |
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219 | str r1, [r0] /* Chip Select 3 */ |
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220 | |
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221 | /* Next, Enable the RS232 Line Drivers in the FPGA. */ |
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222 | /* Also, power on the audio CODEC's amplifier here, */ |
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223 | /* which will make a noise on the audio output. */ |
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224 | /* This is done here instead of in the kernel so there */ |
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225 | /* isn't a loud popping noise at the start of each */ |
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226 | /* song. */ |
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227 | /* Also, disable the CODEC's clocks. */ |
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228 | /* omap1510-HelenP1 [specific] */ |
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229 | |
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230 | ldr r0, REG_FPGA_POWER |
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231 | mov r1, #0 |
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232 | ldr r2, REG_FPGA_DIP_SWITCH |
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233 | ldrb r3, [r2] |
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234 | cmp r3, #0x8 |
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235 | movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */ |
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236 | strb r1, [r0] |
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237 | ldr r0, REG_FPGA_AUDIO |
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238 | mov r1, #0x0 /* Disable sound driver (CODEC clocks) */ |
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239 | strb r1, [r0] |
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240 | |
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241 | /* back to arch calling code */ |
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242 | mov pc, lr |
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243 | |
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244 | /* the literal pools origin */ |
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245 | .ltorg |
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246 | |
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247 | /* OMAP configuration registers */ |
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248 | REG_FUNC_MUX_CTRL_0: /* 32 bits */ |
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249 | .word 0xfffe1000 |
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250 | REG_FUNC_MUX_CTRL_1: /* 32 bits */ |
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251 | .word 0xfffe1004 |
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252 | REG_FUNC_MUX_CTRL_2: /* 32 bits */ |
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253 | .word 0xfffe1008 |
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254 | REG_COMP_MODE_CTRL_0: /* 32 bits */ |
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255 | .word 0xfffe100c |
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256 | REG_FUNC_MUX_CTRL_3: /* 32 bits */ |
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257 | .word 0xfffe1010 |
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258 | REG_FUNC_MUX_CTRL_4: /* 32 bits */ |
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259 | .word 0xfffe1014 |
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260 | REG_FUNC_MUX_CTRL_5: /* 32 bits */ |
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261 | .word 0xfffe1018 |
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262 | REG_FUNC_MUX_CTRL_6: /* 32 bits */ |
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263 | .word 0xfffe101c |
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264 | REG_FUNC_MUX_CTRL_7: /* 32 bits */ |
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265 | .word 0xfffe1020 |
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266 | REG_FUNC_MUX_CTRL_8: /* 32 bits */ |
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267 | .word 0xfffe1024 |
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268 | REG_FUNC_MUX_CTRL_9: /* 32 bits */ |
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269 | .word 0xfffe1028 |
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270 | REG_FUNC_MUX_CTRL_A: /* 32 bits */ |
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271 | .word 0xfffe102C |
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272 | REG_FUNC_MUX_CTRL_B: /* 32 bits */ |
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273 | .word 0xfffe1030 |
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274 | REG_FUNC_MUX_CTRL_C: /* 32 bits */ |
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275 | .word 0xfffe1034 |
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276 | REG_FUNC_MUX_CTRL_D: /* 32 bits */ |
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277 | .word 0xfffe1038 |
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278 | REG_PULL_DWN_CTRL_0: /* 32 bits */ |
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279 | .word 0xfffe1040 |
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280 | REG_PULL_DWN_CTRL_1: /* 32 bits */ |
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281 | .word 0xfffe1044 |
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282 | REG_PULL_DWN_CTRL_2: /* 32 bits */ |
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283 | .word 0xfffe1048 |
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284 | REG_PULL_DWN_CTRL_3: /* 32 bits */ |
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285 | .word 0xfffe104c |
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286 | REG_VOLTAGE_CTRL_0: /* 32 bits */ |
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287 | .word 0xfffe1060 |
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288 | REG_TEST_DBG_CTRL_0: /* 32 bits */ |
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289 | .word 0xfffe1070 |
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290 | REG_MOD_CONF_CTRL_0: /* 32 bits */ |
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291 | .word 0xfffe1080 |
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292 | REG_TC_IMIF_PRIO: /* 32 bits */ |
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293 | .word 0xfffecc00 |
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294 | REG_TC_EMIFS_PRIO: /* 32 bits */ |
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295 | .word 0xfffecc04 |
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296 | REG_TC_EMIFF_PRIO: /* 32 bits */ |
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297 | .word 0xfffecc08 |
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298 | REG_TC_EMIFS_CONFIG: /* 32 bits */ |
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299 | .word 0xfffecc0c |
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300 | REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ |
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301 | .word 0xfffecc10 |
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302 | REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ |
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303 | .word 0xfffecc14 |
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304 | REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ |
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305 | .word 0xfffecc18 |
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306 | REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ |
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307 | .word 0xfffecc1c |
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308 | REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */ |
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309 | .word 0xfffecc20 |
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310 | REG_TC_EMIFF_MRS: /* 32 bits */ |
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311 | .word 0xfffecc24 |
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312 | /* MPU clock/reset/power mode control registers */ |
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313 | REG_ARM_CKCTL: /* 16 bits */ |
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314 | .word 0xfffece00 |
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315 | REG_ARM_IDLECT2: /* 16 bits */ |
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316 | .word 0xfffece08 |
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317 | REG_ARM_RSTCT2: /* 16 bits */ |
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318 | .word 0xfffece14 |
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319 | REG_ARM_SYSST: /* 16 bits */ |
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320 | .word 0xfffece18 |
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321 | /* DPLL control registers */ |
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322 | REG_DPLL1_CTL: /* 16 bits */ |
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323 | .word 0xfffecf00 |
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324 | /* identification code register */ |
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325 | REG_IDCODE: /* 32 bits */ |
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326 | .word 0xfffed404 |
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327 | |
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328 | /* Innovator specific */ |
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329 | REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */ |
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330 | .word 0x08000003 |
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331 | REG_FPGA_POWER: /* 8 bits */ |
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332 | .word 0x08000005 |
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333 | REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */ |
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334 | .word 0x0800000c |
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335 | REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */ |
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336 | .word 0x0800000e |
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337 | |
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338 | VAL_COMP_MODE_CTRL_0: |
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339 | .word 0x0000eaef |
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340 | VAL_FUNC_MUX_CTRL_4: |
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341 | .word 0x00000000 |
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342 | VAL_FUNC_MUX_CTRL_5: |
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343 | .word 0x00000000 |
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344 | VAL_FUNC_MUX_CTRL_6: |
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345 | .word 0x00000001 |
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346 | VAL_FUNC_MUX_CTRL_7: |
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347 | .word 0x00000000 |
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348 | VAL_FUNC_MUX_CTRL_8: |
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349 | .word 0x10001200 |
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350 | VAL_FUNC_MUX_CTRL_9: |
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351 | .word 0x01201012 |
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352 | VAL_FUNC_MUX_CTRL_A: |
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353 | .word 0x00000248 |
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354 | VAL_FUNC_MUX_CTRL_B: |
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355 | .word 0x00000248 |
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356 | VAL_FUNC_MUX_CTRL_C: |
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357 | .word 0x09000000 |
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358 | VAL_FUNC_MUX_CTRL_D: |
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359 | .word 0x00000000 |
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360 | VAL_PULL_DWN_CTRL_0: |
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361 | .word 0x11a10000 |
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362 | VAL_PULL_DWN_CTRL_1: |
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363 | .word 0x2e047fff |
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364 | VAL_PULL_DWN_CTRL_2: |
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365 | .word 0xffd603a6 |
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366 | VAL_PULL_DWN_CTRL_3: |
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367 | .word 0x00003e03 |
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368 | VAL_VOLTAGE_CTRL_0: |
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369 | .word 0x00000007 |
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370 | VAL_TEST_DBG_CTRL_0: |
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371 | /* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 . |
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372 | * This slows down internal SRAM accesses. |
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373 | */ |
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374 | .word 0x00000007 |
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375 | VAL_MOD_CONF_CTRL_0: |
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376 | .word 0x0b000008 |
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377 | VAL_ARM_CKCTL: |
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378 | .word 0x010f |
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379 | VAL_DPLL1_CTL: |
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380 | .word 0x2710 |
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381 | VAL_TC_EMIFS_CS1_CONFIG_PRELIM: |
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382 | .word 0x00001149 |
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383 | VAL_TC_EMIFS_CS2_CONFIG_PRELIM: |
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384 | .word 0x00004158 |
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385 | VAL_TC_EMIFS_CS0_CONFIG: |
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386 | .word 0x002130b0 |
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387 | VAL_TC_EMIFS_CS1_CONFIG: |
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388 | .word 0x0000f559 |
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389 | VAL_TC_EMIFS_CS2_CONFIG: |
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390 | .word 0x000055f0 |
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391 | VAL_TC_EMIFS_CS3_CONFIG: |
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392 | .word 0x00003331 |
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393 | VAL_TC_EMIFF_SDRAM_CONFIG: |
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394 | .word 0x010290fc |
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395 | VAL_TC_EMIFF_MRS: |
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396 | .word 0x00000027 |
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