source: SVN/rincon/u-boot/board/pcippc2/pcippc2_fpga.h @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 1.5 KB
Line 
1/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef _PCIPPC2_FPGA_H_
25#define _PCIPPC2_FPGA_H_
26
27#define FPGA_VENDOR_ID                  0x1310
28#define FPGA_DEVICE_ID                  0x000d
29
30#define HW_FPGA0_INT                    0x0000
31#define HW_FPGA0_BOARD          0x0060
32#define HW_FPGA0_UART1                  0x0080
33#define HW_FPGA0_UART2                  0x0100
34#define HW_FPGA0_RTC                    0x2000
35#define HW_FPGA0_DOC                    0x4000
36#define HW_FPGA1_RTC                    0x0000
37#define HW_FPGA1_DOC                    0x4000
38
39#define HW_FPGA0_INT_INTR_MASK          0x30
40#define HW_FPGA0_INT_INTR_STATUS        0x34
41#define HW_FPGA0_INT_INTR_EOI           0x40
42#define HW_FPGA0_INT_SERIAL_CONFIG      0x5c
43
44#define HW_FPGA0_WDT_CTRL               0x44
45#define HW_FPGA0_WDT_PROG               0x48
46#define HW_FPGA0_WDT_VAL                0x4c
47#define HW_FPGA0_WDT_REFRESH            0x50
48
49#endif
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