source: SVN/rincon/u-boot/board/pm856/tlb.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.7 KB
Line 
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30        /* TLB 0 - for temp stack in cache */
31        SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
32                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
33                      0, 0, BOOKE_PAGESZ_4K, 0),
34        SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
35                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
36                      0, 0, BOOKE_PAGESZ_4K, 0),
37        SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
38                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
39                      0, 0, BOOKE_PAGESZ_4K, 0),
40        SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
41                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
42                      0, 0, BOOKE_PAGESZ_4K, 0),
43
44        /*
45         * TLB 0:       64M     Non-cacheable, guarded
46         * 0xfc000000   64M     FLASH (8,16,32 or 64 MB)
47         * Out of reset this entry is only 4K.
48         */
49        SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
50                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51                      0, 0, BOOKE_PAGESZ_16M, 1),
52
53        /*
54         * TLB 1:       256M    Non-cacheable, guarded
55         * 0x80000000   256M    PCI1 MEM First half
56         */
57        SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
58                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59                      0, 1, BOOKE_PAGESZ_256M, 1),
60
61        /*
62         * TLB 2:       256M    Non-cacheable, guarded
63         * 0x90000000   256M    PCI1 MEM Second half
64         */
65        SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
66                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67                      0, 2, BOOKE_PAGESZ_256M, 1),
68
69        /*
70         * TLB 3:       256M    Non-cacheable, guarded
71         * 0xc0000000   256M    Rapid IO MEM First half
72         */
73        SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
74                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
75                      0, 3, BOOKE_PAGESZ_256M, 1),
76
77        /*
78         * TLB 4:       256M    Non-cacheable, guarded
79         * 0xd0000000   256M    Rapid IO MEM Second half
80         */
81        SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
82                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83                      0, 4, BOOKE_PAGESZ_256M, 1),
84
85        /*
86         * TLB 5:       64M     Non-cacheable, guarded
87         * 0xe000_0000  1M      CCSRBAR
88         * 0xe200_0000  16M     PCI1 IO
89         */
90        SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
91                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92                      0, 5, BOOKE_PAGESZ_64M, 1),
93
94        /*
95         * TLB 6:       64M     Cacheable, non-guarded
96         * 0xf000_0000  64M     LBC SDRAM
97         */
98        SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
99                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
100                      0, 6, BOOKE_PAGESZ_64M, 1),
101
102#if !defined(CONFIG_SPD_EEPROM)
103        /*
104         * TLB 7:       256M    DDR
105         * 0x00000000   256M    DDR System memory
106         * Without SPD EEPROM configured DDR, this must be setup manually.
107         * Make sure the TLB count at the top of this table is correct.
108         * Likely it needs to be increased by two for these entries.
109         */
110
111        SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
112                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
113                      0, 7, BOOKE_PAGESZ_256M, 1),
114#endif
115};
116
117int num_tlb_entries = ARRAY_SIZE(tlb_table);
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