source: SVN/rincon/u-boot/board/prodrive/alpr/nand.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 23 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.7 KB
RevLine 
[55]1/*
2 * (C) Copyright 2006
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de
4 *
5 * (C) Copyright 2006
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28
29#if defined(CONFIG_CMD_NAND)
30
31#include <asm/processor.h>
32#include <nand.h>
33
34struct alpr_ndfc_regs {
35        u8 cmd[4];
36        u8 addr_wait;
37        u8 term;
38        u8 dummy;
39        u8 dummy2;
40        u8 data;
41};
42
43static u8 hwctl;
44static struct alpr_ndfc_regs *alpr_ndfc = NULL;
45
46#define readb(addr)     (u8)(*(volatile u8 *)(addr))
47#define writeb(d,addr)  *(volatile u8 *)(addr) = ((u8)(d))
48
49/*
50 * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
51 * the NAND devices.  The NDFC has command, address and data registers that
52 * when accessed will set up the NAND flash pins appropriately.  We'll use the
53 * hwcontrol function to save the configuration in a global variable.
54 * We can then use this information in the read and write functions to
55 * determine which NDFC register to access.
56 *
57 * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
58 */
59static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
60{
61        struct nand_chip *this = mtd->priv;
62
63        if (ctrl & NAND_CTRL_CHANGE) {
64                if ( ctrl & NAND_CLE )
65                        hwctl |= 0x1;
66                else
67                        hwctl &= ~0x1;
68                if ( ctrl & NAND_ALE )
69                        hwctl |= 0x2;
70                else
71                        hwctl &= ~0x2;
72                if ( (ctrl & NAND_NCE) != NAND_NCE)
73                        writeb(0x00, &(alpr_ndfc->term));
74        }
75        if (cmd != NAND_CMD_NONE)
76                writeb(cmd, this->IO_ADDR_W);
77}
78
79static u_char alpr_nand_read_byte(struct mtd_info *mtd)
80{
81        return readb(&(alpr_ndfc->data));
82}
83
84static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
85{
86        struct nand_chip *nand = mtd->priv;
87        int i;
88
89        for (i = 0; i < len; i++) {
90                if (hwctl & 0x1)
91                         /*
92                          * IO_ADDR_W used as CMD[i] reg to support multiple NAND
93                          * chips.
94                          */
95                        writeb(buf[i], nand->IO_ADDR_W);
96                else if (hwctl & 0x2)
97                        writeb(buf[i], &(alpr_ndfc->addr_wait));
98                else
99                        writeb(buf[i], &(alpr_ndfc->data));
100        }
101}
102
103static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
104{
105        int i;
106
107        for (i = 0; i < len; i++) {
108                buf[i] = readb(&(alpr_ndfc->data));
109        }
110}
111
112static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
113{
114        int i;
115
116        for (i = 0; i < len; i++)
117                if (buf[i] != readb(&(alpr_ndfc->data)))
118                        return i;
119
120        return 0;
121}
122
123static int alpr_nand_dev_ready(struct mtd_info *mtd)
124{
125        volatile u_char val;
126
127        /*
128         * Blocking read to wait for NAND to be ready
129         */
130        val = readb(&(alpr_ndfc->addr_wait));
131
132        /*
133         * Return always true
134         */
135        return 1;
136}
137
138int board_nand_init(struct nand_chip *nand)
139{
140        alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
141
142        nand->ecc.mode = NAND_ECC_SOFT;
143
144        /* Reference hardware control function */
145        nand->cmd_ctrl  = alpr_nand_hwcontrol;
146        nand->read_byte  = alpr_nand_read_byte;
147        nand->write_buf  = alpr_nand_write_buf;
148        nand->read_buf   = alpr_nand_read_buf;
149        nand->verify_buf = alpr_nand_verify_buf;
150        nand->dev_ready  = alpr_nand_dev_ready;
151
152        return 0;
153}
154#endif
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