source: SVN/rincon/u-boot/board/prodrive/p3p440/p3p440.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 7.8 KB
Line 
1/*
2 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/processor.h>
28#include <command.h>
29
30#include "p3p440.h"
31
32DECLARE_GLOBAL_DATA_PTR;
33
34void set_led(int color)
35{
36        switch (color) {
37        case LED_OFF:
38                out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
39                break;
40
41        case LED_GREEN:
42                out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
43                break;
44
45        case LED_RED:
46                out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
47                break;
48
49        case LED_ORANGE:
50                out32(GPIO0_OR,  in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
51                break;
52        }
53}
54
55static int is_monarch(void)
56{
57        out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_GPIO_RDY);
58        udelay(1000);
59
60        if (in32(GPIO0_IR) & CFG_MONARCH_IO)
61                return 0;
62        else
63                return 1;
64}
65
66static void wait_for_pci_ready(void)
67{
68        /*
69         * Configure EREADY_IO as input
70         */
71        out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
72        udelay(1000);
73
74        for (;;) {
75                if (in32(GPIO0_IR) & CFG_EREADY_IO)
76                        return;
77        }
78
79}
80
81int board_early_init_f(void)
82{
83        uint reg;
84
85        /*--------------------------------------------------------------------
86         * Setup the external bus controller/chip selects
87         *-------------------------------------------------------------------*/
88        mtdcr(ebccfga, xbcfg);
89        reg = mfdcr(ebccfgd);
90        mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
91
92        /*--------------------------------------------------------------------
93         * Setup pin multiplexing (GPIO/IRQ...)
94         *-------------------------------------------------------------------*/
95        mtdcr(cpc0_gpio, 0x03F01F80);
96
97        out32(GPIO0_ODR, 0x00000000);   /* no open drain pins      */
98        out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
99        out32(GPIO0_OR,  CFG_GPIO_RDY);
100
101        /*--------------------------------------------------------------------
102         * Setup the interrupt controller polarities, triggers, etc.
103         *-------------------------------------------------------------------*/
104        mtdcr(uic0sr, 0xffffffff);      /* clear all */
105        mtdcr(uic0er, 0x00000000);      /* disable all */
106        mtdcr(uic0cr, 0x00000001);      /* UIC1 crit is critical */
107        mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
108        mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
109        mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
110        mtdcr(uic0sr, 0xffffffff);      /* clear all */
111
112        mtdcr(uic1sr, 0xffffffff);      /* clear all */
113        mtdcr(uic1er, 0x00000000);      /* disable all */
114        mtdcr(uic1cr, 0x00000000);      /* all non-critical */
115        mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
116        mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
117        mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
118        mtdcr(uic1sr, 0xffffffff);      /* clear all */
119
120        return 0;
121}
122
123int checkboard(void)
124{
125        char *s = getenv("serial#");
126
127        printf("Board: P3P440");
128        if (s != NULL) {
129                puts(", serial# ");
130                puts(s);
131        }
132
133        if (is_monarch()) {
134                puts(", Monarch");
135        } else {
136                puts(", None-Monarch");
137        }
138
139        putc('\n');
140
141        return (0);
142}
143
144int misc_init_r (void)
145{
146        /*
147         * Adjust flash start and offset to detected values
148         */
149        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
150        gd->bd->bi_flashoffset = 0;
151
152        /*
153         * Check if only one FLASH bank is available
154         */
155        if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
156                mtebc(pb1cr, 0);                        /* disable cs */
157                mtebc(pb1ap, 0);
158                mtebc(pb2cr, 0);                        /* disable cs */
159                mtebc(pb2ap, 0);
160                mtebc(pb3cr, 0);                        /* disable cs */
161                mtebc(pb3ap, 0);
162        }
163
164        return 0;
165}
166
167/*************************************************************************
168 *  pci_pre_init
169 *
170 *  This routine is called just prior to registering the hose and gives
171 *  the board the opportunity to check things. Returning a value of zero
172 *  indicates that things are bad & PCI initialization should be aborted.
173 *
174 *      Different boards may wish to customize the pci controller structure
175 *      (add regions, override default access routines, etc) or perform
176 *      certain pre-initialization actions.
177 *
178 ************************************************************************/
179#if defined(CONFIG_PCI)
180int pci_pre_init(struct pci_controller *hose)
181{
182        unsigned long strap;
183
184        /*--------------------------------------------------------------------------+
185         *      The P3P440 board is always configured as the host & requires the
186         *      PCI arbiter to be disabled because it's an PMC module.
187         *--------------------------------------------------------------------------*/
188        strap = mfdcr(cpc0_strp1);
189        if (strap & 0x00100000) {
190                printf("PCI: CPC0_STRP1[PAE] set.\n");
191                return 0;
192        }
193
194        return 1;
195}
196#endif  /* defined(CONFIG_PCI) */
197
198/*************************************************************************
199 *  pci_target_init
200 *
201 *      The bootstrap configuration provides default settings for the pci
202 *      inbound map (PIM). But the bootstrap config choices are limited and
203 *      may not be sufficient for a given board.
204 *
205 ************************************************************************/
206#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
207void pci_target_init(struct pci_controller *hose)
208{
209        /*--------------------------------------------------------------------------+
210         * Disable everything
211         *--------------------------------------------------------------------------*/
212        out32r(PCIX0_PIM0SA, 0);        /* disable */
213        out32r(PCIX0_PIM1SA, 0);        /* disable */
214        out32r(PCIX0_PIM2SA, 0);        /* disable */
215        out32r(PCIX0_EROMBA, 0);        /* disable expansion rom */
216
217        /*--------------------------------------------------------------------------+
218         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
219         * options to not support sizes such as 128/256 MB.
220         *--------------------------------------------------------------------------*/
221        out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
222        out32r(PCIX0_PIM0LAH, 0);
223        out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
224
225        out32r(PCIX0_BAR0, 0);
226
227        /*--------------------------------------------------------------------------+
228         * Program the board's subsystem id/vendor id
229         *--------------------------------------------------------------------------*/
230        out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
231        out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
232
233        out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
234}
235#endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
236
237/*************************************************************************
238 *  is_pci_host
239 *
240 *      This routine is called to determine if a pci scan should be
241 *      performed. With various hardware environments (especially cPCI and
242 *      PPMC) it's insufficient to depend on the state of the arbiter enable
243 *      bit in the strap register, or generic host/adapter assumptions.
244 *
245 *      Rather than hard-code a bad assumption in the general 440 code, the
246 *      440 pci code requires the board to decide at runtime.
247 *
248 *      Return 0 for adapter mode, non-zero for host (monarch) mode.
249 *
250 *
251 ************************************************************************/
252#if defined(CONFIG_PCI)
253int is_pci_host(struct pci_controller *hose)
254{
255        if (is_monarch()) {
256                wait_for_pci_ready();
257                return 1;               /* return 1 for host controller */
258        } else {
259                return 0;               /* return 0 for adapter controller */
260        }
261}
262#endif                          /* defined(CONFIG_PCI) */
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