source: SVN/rincon/u-boot/board/pxa255_idp/idp_notes.txt @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 1.3 KB
Line 
1Notes on the Vibren PXA255 IDP.
2
3Chip select usage:
4
5CS0 - flash
6CS1 - alt flash (Mdoc or main flash)
7CS2 - high speed expansion bus
8CS3 - Media Q, low speed exp bus
9CS4 - low speed exp bus
10CS5 - low speed exp bus
11  - IDE: offset 0x03000000 (abs: 0x17000000)
12  - Eth: offset 0x03400000 (abs: 0x17400000)
13  - core voltage latch: offset 0x03800000 (abs: 0x17800000)
14  - CPLD: offset 0x03C00000 (abs: 0x17C00000)
15
16PCMCIA Power control
17
18MAX1602EE w/ code pulled high (Cirrus code)
19vx = 5v
20vy = 3v
21
22                        Bit pattern
23                        PWR 3,2,1,0
24vcc          vpp        A1VCC  A0VCC   A1VPP   A0VPP
25=====================================================
260            0            0      0       0       0      0x0
273 (vy)       0            1      0       1       1      0xB
283 (vy)       3 (vy)       1      0       0       1      0x9
293 (vy)       12(12in)     1      0       1       0      0xA
305 (vx)       0            0      1       1       1      0x7
315 (vx)       5 (vx)       0      1       0       1      0x5
325 (vx        12(12in)     0      1       1       0      0x6
33
34Display power sequencing:
35
36- VDD applied
37- within 1sec, activate scanning signals
38- wait at least 50mS - scanning signals must be active before activating DISP
39
40Signal mapping:
41Schematic            LV8V31 signal name
42=========================================
43LCD_ENAVLCD             DISP
44LCD_PWR                 Applies VDD to board
45
46Both of the above signals are controlled by the CPLD
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