| 1 | /* |
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| 2 | * Copyright (C) 2007 Nobuhiro Iwamatsu |
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| 3 | * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> |
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| 4 | * |
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| 5 | * u-boot/board/r7780mp/r7780mp.h |
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| 6 | * |
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| 7 | * This program is free software; you can redistribute it and/or |
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| 8 | * modify it under the terms of the GNU General Public License as |
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| 9 | * published by the Free Software Foundation; either version 2 of |
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| 10 | * the License, or (at your option) any later version. |
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| 11 | * |
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| 12 | * This program is distributed in the hope that it will be useful, |
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| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 15 | * GNU General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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| 18 | * along with this program; if not, write to the Free Software |
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| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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| 20 | * MA 02111-1307 USA |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef _BOARD_R7780MP_R7780MP_H_ |
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| 24 | #define _BOARD_R7780MP_R7780MP_H_ |
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| 25 | |
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| 26 | /* R7780MP's FPGA register map */ |
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| 27 | #define FPGA_BASE 0xa4000000 |
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| 28 | #define FPGA_IRLMSK (FPGA_BASE + 0x00) |
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| 29 | #define FPGA_IRLMON (FPGA_BASE + 0x02) |
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| 30 | #define FPGA_IRLPRI1 (FPGA_BASE + 0x04) |
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| 31 | #define FPGA_IRLPRI2 (FPGA_BASE + 0x06) |
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| 32 | #define FPGA_IRLPRI3 (FPGA_BASE + 0x08) |
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| 33 | #define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) |
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| 34 | #define FPGA_RSTCTL (FPGA_BASE + 0x0C) |
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| 35 | #define FPGA_PCIBD (FPGA_BASE + 0x0E) |
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| 36 | #define FPGA_PCICD (FPGA_BASE + 0x10) |
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| 37 | #define FPGA_EXTGIO (FPGA_BASE + 0x16) |
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| 38 | #define FPGA_IVDRMON (FPGA_BASE + 0x18) |
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| 39 | #define FPGA_IVDRCR (FPGA_BASE + 0x1A) |
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| 40 | #define FPGA_OBLED (FPGA_BASE + 0x1C) |
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| 41 | #define FPGA_OBSW (FPGA_BASE + 0x1E) |
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| 42 | #define FPGA_TPCTL (FPGA_BASE + 0x100) |
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| 43 | #define FPGA_TPDCKCTL (FPGA_BASE + 0x102) |
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| 44 | #define FPGA_TPCLR (FPGA_BASE + 0x104) |
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| 45 | #define FPGA_TPXPOS (FPGA_BASE + 0x106) |
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| 46 | #define FPGA_TPYPOS (FPGA_BASE + 0x108) |
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| 47 | #define FPGA_DBSW (FPGA_BASE + 0x200) |
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| 48 | #define FPGA_VERSION (FPGA_BASE + 0x700) |
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| 49 | #define FPGA_CFCTL (FPGA_BASE + 0x300) |
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| 50 | #define FPGA_CFPOW (FPGA_BASE + 0x302) |
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| 51 | #define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) |
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| 52 | #define FPGA_PMR (FPGA_BASE + 0x900) |
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| 53 | |
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| 54 | #endif /* _BOARD_R7780RP_R7780RP_H_ */ |
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