source: SVN/rincon/u-boot/board/samsung/smdk6400/lowlevel_init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 3 years ago

rincon: added latest u-boot source

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Signed-off-by: Tim Harvey <tharvey@…>

File size: 6.6 KB
Line 
1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 *
7 * Modified for the Samsung SMDK2410 by
8 * (C) Copyright 2002
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 *
11 * (C) Copyright 2008
12 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33
34#include <config.h>
35#include <version.h>
36
37#include <s3c6400.h>
38
39#ifdef CONFIG_SERIAL1
40#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
41#elif defined(CONFIG_SERIAL2)
42#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
43#else
44#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
45#endif
46
47_TEXT_BASE:
48        .word   TEXT_BASE
49
50        .globl lowlevel_init
51lowlevel_init:
52        mov     r12, lr
53
54        /* LED on only #8 */
55        ldr     r0, =ELFIN_GPIO_BASE
56        ldr     r1, =0x55540000
57        str     r1, [r0, #GPNCON_OFFSET]
58
59        ldr     r1, =0x55555555
60        str     r1, [r0, #GPNPUD_OFFSET]
61
62        ldr     r1, =0xf000
63        str     r1, [r0, #GPNDAT_OFFSET]
64
65        /* Disable Watchdog */
66        ldr     r0, =0x7e000000         @0x7e004000
67        orr     r0, r0, #0x4000
68        mov     r1, #0
69        str     r1, [r0]
70
71        /* External interrupt pending clear */
72        ldr     r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET)  /*EINTPEND*/
73        ldr     r1, [r0]
74        str     r1, [r0]
75
76        ldr     r0, =ELFIN_VIC0_BASE_ADDR       @0x71200000
77        ldr     r1, =ELFIN_VIC1_BASE_ADDR       @0x71300000
78
79        /* Disable all interrupts (VIC0 and VIC1) */
80        mvn     r3, #0x0
81        str     r3, [r0, #oINTMSK]
82        str     r3, [r1, #oINTMSK]
83
84        /* Set all interrupts as IRQ */
85        mov     r3, #0x0
86        str     r3, [r0, #oINTMOD]
87        str     r3, [r1, #oINTMOD]
88
89        /* Pending Interrupt Clear */
90        mov     r3, #0x0
91        str     r3, [r0, #oVECTADDR]
92        str     r3, [r1, #oVECTADDR]
93
94        /* init system clock */
95        bl system_clock_init
96
97#ifndef CONFIG_NAND_SPL
98        /* for UART */
99        bl uart_asm_init
100#endif
101
102#ifdef CONFIG_BOOT_NAND
103        /* simple init for NAND */
104        bl nand_asm_init
105#endif
106
107        bl      mem_ctrl_asm_init
108
109/* Wakeup support. Don't know if it's going to be used, untested. */
110        ldr     r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
111        ldr     r1, [r0]
112        bic     r1, r1, #0xfffffff7
113        cmp     r1, #0x8
114        beq     wakeup_reset
115
1161:
117        mov     lr, r12
118        mov     pc, lr
119
120wakeup_reset:
121
122        /* Clear wakeup status register */
123        ldr     r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
124        ldr     r1, [r0]
125        str     r1, [r0]
126
127        /* LED test */
128        ldr     r0, =ELFIN_GPIO_BASE
129        ldr     r1, =0x3000
130        str     r1, [r0, #GPNDAT_OFFSET]
131
132        /* Load return address and jump to kernel */
133        ldr     r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
134        /* r1 = physical address of s3c6400_cpu_resume function */
135        ldr     r1, [r0]
136        /* Jump to kernel (sleep-s3c6400.S) */
137        mov     pc, r1
138        nop
139        nop
140/*
141 * system_clock_init: Initialize core clock and bus clock.
142 * void system_clock_init(void)
143 */
144system_clock_init:
145        ldr     r0, =ELFIN_CLOCK_POWER_BASE     /* 0x7e00f000 */
146
147#ifdef CONFIG_SYNC_MODE
148        ldr     r1, [r0, #OTHERS_OFFSET]
149        mov     r2, #0x40
150        orr     r1, r1, r2
151        str     r1, [r0, #OTHERS_OFFSET]
152
153        nop
154        nop
155        nop
156        nop
157        nop
158
159        ldr     r2, =0x80
160        orr     r1, r1, r2
161        str     r1, [r0, #OTHERS_OFFSET]
162
163check_syncack:
164        ldr     r1, [r0, #OTHERS_OFFSET]
165        ldr     r2, =0xf00
166        and     r1, r1, r2
167        cmp     r1, #0xf00
168        bne     check_syncack
169#else   /* ASYNC Mode */
170        nop
171        nop
172        nop
173        nop
174        nop
175
176        /*
177         * This was unconditional in original Samsung sources, but it doesn't
178         * seem to make much sense on S3C6400.
179         */
180#ifndef CONFIG_S3C6400
181        ldr     r1, [r0, #OTHERS_OFFSET]
182        bic     r1, r1, #0xC0
183        orr     r1, r1, #0x40
184        str     r1, [r0, #OTHERS_OFFSET]
185
186wait_for_async:
187        ldr     r1, [r0, #OTHERS_OFFSET]
188        and     r1, r1, #0xf00
189        cmp     r1, #0x0
190        bne     wait_for_async
191#endif
192
193        ldr     r1, [r0, #OTHERS_OFFSET]
194        bic     r1, r1, #0x40
195        str     r1, [r0, #OTHERS_OFFSET]
196#endif
197
198        mov     r1, #0xff00
199        orr     r1, r1, #0xff
200        str     r1, [r0, #APLL_LOCK_OFFSET]
201        str     r1, [r0, #MPLL_LOCK_OFFSET]
202
203        /* Set Clock Divider */
204        ldr     r1, [r0, #CLK_DIV0_OFFSET]
205        bic     r1, r1, #0x30000
206        bic     r1, r1, #0xff00
207        bic     r1, r1, #0xff
208        ldr     r2, =CLK_DIV_VAL
209        orr     r1, r1, r2
210        str     r1, [r0, #CLK_DIV0_OFFSET]
211
212        ldr     r1, =APLL_VAL
213        str     r1, [r0, #APLL_CON_OFFSET]
214        ldr     r1, =MPLL_VAL
215        str     r1, [r0, #MPLL_CON_OFFSET]
216
217        /* FOUT of EPLL is 96MHz */
218        ldr     r1, =0x200203
219        str     r1, [r0, #EPLL_CON0_OFFSET]
220        ldr     r1, =0x0
221        str     r1, [r0, #EPLL_CON1_OFFSET]
222
223        /* APLL, MPLL, EPLL select to Fout */
224        ldr     r1, [r0, #CLK_SRC_OFFSET]
225        orr     r1, r1, #0x7
226        str     r1, [r0, #CLK_SRC_OFFSET]
227
228        /* wait at least 200us to stablize all clock */
229        mov     r1, #0x10000
2301:      subs    r1, r1, #1
231        bne     1b
232
233        /* Synchronization for VIC port */
234#if defined(CONFIG_SYNC_MODE)
235        ldr     r1, [r0, #OTHERS_OFFSET]
236        orr     r1, r1, #0x20
237        str     r1, [r0, #OTHERS_OFFSET]
238#elif !defined(CONFIG_S3C6400)
239        /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
240        ldr     r1, [r0, #OTHERS_OFFSET]
241        bic     r1, r1, #0x20
242        str     r1, [r0, #OTHERS_OFFSET]
243#endif
244        mov     pc, lr
245
246
247#ifndef CONFIG_NAND_SPL
248/*
249 * uart_asm_init: Initialize UART's pins
250 */
251uart_asm_init:
252        /* set GPIO to enable UART */
253        ldr     r0, =ELFIN_GPIO_BASE
254        ldr     r1, =0x220022
255        str     r1, [r0, #GPACON_OFFSET]
256        mov     pc, lr
257#endif
258
259#ifdef CONFIG_BOOT_NAND
260/*
261 * NAND Interface init for SMDK6400
262 */
263nand_asm_init:
264        ldr     r0, =ELFIN_NAND_BASE
265        ldr     r1, [r0, #NFCONF_OFFSET]
266        orr     r1, r1, #0x70
267        orr     r1, r1, #0x7700
268        str     r1, [r0, #NFCONF_OFFSET]
269
270        ldr     r1, [r0, #NFCONT_OFFSET]
271        orr     r1, r1, #0x07
272        str     r1, [r0, #NFCONT_OFFSET]
273
274        mov     pc, lr
275#endif
276
277#ifdef CONFIG_ENABLE_MMU
278/*
279 * MMU Table for SMDK6400
280 */
281
282        /* form a first-level section entry */
283.macro FL_SECTION_ENTRY base,ap,d,c,b
284        .word (\base << 20) | (\ap << 10) | \
285              (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
286.endm
287
288.section .mmudata, "a"
289        .align 14
290        /* the following alignment creates the mmu table at address 0x4000. */
291        .globl mmu_table
292mmu_table:
293        .set __base, 0
294        /* 1:1 mapping for debugging */
295        .rept 0xA00
296        FL_SECTION_ENTRY __base, 3, 0, 0, 0
297        .set __base, __base + 1
298        .endr
299
300        /* access is not allowed. */
301        .rept 0xC00 - 0xA00
302        .word 0x00000000
303        .endr
304
305        /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
306        .set __base, 0x500
307        .rept 0xC80 - 0xC00
308        FL_SECTION_ENTRY __base, 3, 0, 1, 1
309        .set __base, __base + 1
310        .endr
311
312        /* access is not allowed. */
313        .rept 0x1000 - 0xc80
314        .word 0x00000000
315        .endr
316#endif
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