source: SVN/rincon/u-boot/board/sbc2410x/sbc2410x.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 4.1 KB
Line 
1/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2005
10 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <common.h>
32#include <s3c2410.h>
33
34#if defined(CONFIG_CMD_NAND)
35#include <linux/mtd/nand.h>
36#endif
37
38DECLARE_GLOBAL_DATA_PTR;
39
40#define FCLK_SPEED 1
41
42#if FCLK_SPEED==0               /* Fout = 203MHz, Fin = 12MHz for Audio */
43#define M_MDIV  0xC3
44#define M_PDIV  0x4
45#define M_SDIV  0x1
46#elif FCLK_SPEED==1             /* Fout = 202.8MHz */
47#define M_MDIV  0x5c
48#define M_PDIV  0x4
49#define M_SDIV  0x0
50#endif
51
52#define USB_CLOCK 1
53
54#if USB_CLOCK==0
55#define U_M_MDIV        0xA1
56#define U_M_PDIV        0x3
57#define U_M_SDIV        0x1
58#elif USB_CLOCK==1
59#define U_M_MDIV        0x48
60#define U_M_PDIV        0x3
61#define U_M_SDIV        0x2
62#endif
63
64static inline void delay (unsigned long loops)
65{
66        __asm__ volatile ("1:\n"
67                          "subs %0, %1, #1\n"
68                          "bne 1b":"=r" (loops):"0" (loops));
69}
70
71/*
72 * Miscellaneous platform dependent initialisations
73 */
74
75int board_init (void)
76{
77        S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
78        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
79
80        /* to reduce PLL lock time, adjust the LOCKTIME register */
81        clk_power->LOCKTIME = 0xFFFFFF;
82
83        /* configure MPLL */
84        clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
85
86        /* some delay between MPLL and UPLL */
87        delay (4000);
88
89        /* configure UPLL */
90        clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
91
92        /* some delay between MPLL and UPLL */
93        delay (8000);
94
95        /* set up the I/O ports */
96        gpio->GPACON = 0x007FFFFF;
97        gpio->GPBCON = 0x00044556;
98        gpio->GPBUP = 0x000007FF;
99        gpio->GPCCON = 0xAAAAAAAA;
100        gpio->GPCUP = 0x0000FFFF;
101        gpio->GPDCON = 0xAAAAAAAA;
102        gpio->GPDUP = 0x0000FFFF;
103        gpio->GPECON = 0xAAAAAAAA;
104        gpio->GPEUP = 0x0000FFFF;
105        gpio->GPFCON = 0x000055AA;
106        gpio->GPFUP = 0x000000FF;
107        gpio->GPGCON = 0xFF95FF3A;
108        gpio->GPGUP = 0x0000FFFF;
109        gpio->GPHCON = 0x0016FAAA;
110        gpio->GPHUP = 0x000007FF;
111
112        gpio->EXTINT0=0x22222222;
113        gpio->EXTINT1=0x22222222;
114        gpio->EXTINT2=0x22222222;
115
116        /* arch number of SMDK2410-Board */
117        gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
118
119        /* adress of boot parameters */
120        gd->bd->bi_boot_params = 0x30000100;
121
122        icache_enable();
123        dcache_enable();
124
125        return 0;
126}
127
128int dram_init (void)
129{
130        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
131        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
132
133        return 0;
134}
135
136#if defined(CONFIG_CMD_NAND)
137extern ulong nand_probe(ulong physadr);
138
139static inline void NF_Reset(void)
140{
141        int i;
142
143        NF_SetCE(NFCE_LOW);
144        NF_Cmd(0xFF);           /* reset command */
145        for(i = 0; i < 10; i++);        /* tWB = 100ns. */
146        NF_WaitRB();            /* wait 200~500us; */
147        NF_SetCE(NFCE_HIGH);
148}
149
150static inline void NF_Init(void)
151{
152#if 1
153#define TACLS   0
154#define TWRPH0  3
155#define TWRPH1  0
156#else
157#define TACLS   0
158#define TWRPH0  4
159#define TWRPH1  2
160#endif
161
162        NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
163        /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
164        /* 1  1    1     1,   1      xxx,  r xxx,   r xxx */
165        /* En 512B 4step ECCR nFCE=H tACLS   tWRPH0   tWRPH1 */
166
167        NF_Reset();
168}
169
170void nand_init(void)
171{
172        S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
173
174        NF_Init();
175#ifdef DEBUG
176        printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
177#endif
178        printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
179}
180#endif
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