1 | /* |
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2 | * Copyright 2008 Freescale Semiconductor, Inc. |
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3 | * |
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4 | * This program is free software; you can redistribute it and/or |
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5 | * modify it under the terms of the GNU General Public License |
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6 | * Version 2 as published by the Free Software Foundation. |
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7 | */ |
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8 | |
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9 | #include <common.h> |
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10 | #include <i2c.h> |
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11 | |
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12 | #include <asm/fsl_ddr_sdram.h> |
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13 | |
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14 | static void |
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15 | get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) |
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16 | { |
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17 | i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); |
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18 | } |
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19 | |
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20 | unsigned int fsl_ddr_get_mem_data_rate(void) |
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21 | { |
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22 | return get_bus_freq(0); |
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23 | } |
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24 | |
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25 | void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, |
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26 | unsigned int ctrl_num) |
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27 | { |
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28 | unsigned int i; |
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29 | unsigned int i2c_address = 0; |
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30 | |
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31 | for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { |
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32 | if (ctrl_num == 0 && i == 0) { |
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33 | i2c_address = SPD_EEPROM_ADDRESS1; |
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34 | } |
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35 | if (ctrl_num == 0 && i == 1) { |
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36 | i2c_address = SPD_EEPROM_ADDRESS2; |
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37 | } |
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38 | if (ctrl_num == 1 && i == 0) { |
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39 | i2c_address = SPD_EEPROM_ADDRESS3; |
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40 | } |
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41 | if (ctrl_num == 1 && i == 1) { |
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42 | i2c_address = SPD_EEPROM_ADDRESS4; |
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43 | } |
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44 | get_spd(&(ctrl_dimms_spd[i]), i2c_address); |
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45 | } |
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46 | } |
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47 | |
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48 | void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) |
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49 | { |
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50 | /* |
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51 | * Factors to consider for clock adjust: |
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52 | * - number of chips on bus |
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53 | * - position of slot |
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54 | * - DDR1 vs. DDR2? |
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55 | * - ??? |
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56 | * |
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57 | * This needs to be determined on a board-by-board basis. |
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58 | * 0110 3/4 cycle late |
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59 | * 0111 7/8 cycle late |
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60 | */ |
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61 | popts->clk_adjust = 7; |
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62 | |
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63 | /* |
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64 | * Factors to consider for CPO: |
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65 | * - frequency |
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66 | * - ddr1 vs. ddr2 |
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67 | */ |
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68 | popts->cpo_override = 10; |
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69 | |
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70 | /* |
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71 | * Factors to consider for write data delay: |
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72 | * - number of DIMMs |
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73 | * |
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74 | * 1 = 1/4 clock delay |
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75 | * 2 = 1/2 clock delay |
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76 | * 3 = 3/4 clock delay |
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77 | * 4 = 1 clock delay |
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78 | * 5 = 5/4 clock delay |
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79 | * 6 = 3/2 clock delay |
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80 | */ |
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81 | popts->write_data_delay = 3; |
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82 | |
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83 | /* |
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84 | * Factors to consider for half-strength driver enable: |
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85 | * - number of DIMMs installed |
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86 | */ |
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87 | popts->half_strength_driver_enable = 0; |
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88 | } |
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