source: SVN/rincon/u-boot/board/socrates/law.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 2.1 KB
Line 
1/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * Copyright 2008 Freescale Semiconductor, Inc.
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <asm/fsl_law.h>
31#include <asm/mmu.h>
32
33/*
34 * LAW(Local Access Window) configuration:
35 *
36 * 0x0000_0000     0x2fff_ffff     DDR                     512M
37 * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
38 * 0xc000_0000     0xc00f_ffff     FPGA                    1M
39 * 0xc800_0000     0xcbff_ffff     LIME                    64M
40 * 0xe000_0000     0xe00f_ffff     CCSR                    1M (mapped by CCSRBAR)
41 * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
42 * 0xfc00_0000     0xffff_ffff     FLASH                   64M
43 *
44 * Notes:
45 *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
46 *    If flash is 8M at default position (last 8M), no LAW needed.
47 */
48
49struct law_entry law_table[] = {
50        SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
51        SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
52        SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
53        SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
54#if defined(CFG_FPGA_BASE)
55        SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
56#endif
57        SET_LAW(CFG_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC),
58};
59
60int num_law_entries = ARRAY_SIZE(law_table);
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