source: SVN/rincon/u-boot/board/trab/rs485.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 4.5 KB
Line 
1/*
2 * (C) Copyright 2003
3 * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
4 *
5 * Based on cpu/arm920t/serial.c, by Gary Jennejohn
6 * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21 *
22 */
23
24#include <common.h>
25#include <s3c2400.h>
26#include "rs485.h"
27
28static void rs485_setbrg (void);
29static void rs485_cfgio (void);
30static void set_rs485re(unsigned char rs485re_state);
31static void set_rs485de(unsigned char rs485de_state);
32static void rs485_setbrg (void);
33#ifdef  NOT_USED
34static void trab_rs485_disable_tx(void);
35static void trab_rs485_disable_rx(void);
36#endif
37
38#define UART_NR S3C24X0_UART1
39
40/* CPLD-Register for controlling TRAB hardware functions */
41#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
42
43static void rs485_setbrg (void)
44{
45        S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
46        int i;
47        unsigned int reg = 0;
48
49        /* value is calculated so : (int)(PCLK/16./baudrate) -1 */
50        /* reg = (33000000 / (16 * gd->baudrate)) - 1; */
51        reg = (33000000 / (16 * 38400)) - 1;
52
53        /* FIFO enable, Tx/Rx FIFO clear */
54        uart->UFCON = 0x07;
55        uart->UMCON = 0x0;
56        /* Normal,No parity,1 stop,8 bit */
57        uart->ULCON = 0x3;
58        /*
59         * tx=level,rx=edge,disable timeout int.,enable rx error int.,
60         * normal,interrupt or polling
61         */
62        uart->UCON = 0x245;
63        uart->UBRDIV = reg;
64
65        for (i = 0; i < 100; i++);
66}
67
68static void rs485_cfgio (void)
69{
70        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
71
72        gpio->PFCON &= ~(0x3 << 2);
73        gpio->PFCON |=  (0x2 << 2); /* configure GPF1 as RXD1 */
74
75        gpio->PFCON &= ~(0x3 << 6);
76        gpio->PFCON |=  (0x2 << 6); /* configure GPF3 as TXD1 */
77
78        gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
79        gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */
80
81        gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
82}
83
84/*
85 * Initialise the rs485 port with the given baudrate. The settings
86 * are always 8 data bits, no parity, 1 stop bit, no start bits.
87 *
88 */
89int rs485_init (void)
90{
91        rs485_cfgio ();
92        rs485_setbrg ();
93
94        return (0);
95}
96
97/*
98 * Read a single byte from the rs485 port. Returns 1 on success, 0
99 * otherwise. When the function is succesfull, the character read is
100 * written into its argument c.
101 */
102int rs485_getc (void)
103{
104        S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
105
106        /* wait for character to arrive */
107        while (!(uart->UTRSTAT & 0x1));
108
109        return uart->URXH & 0xff;
110}
111
112/*
113 * Output a single byte to the rs485 port.
114 */
115void rs485_putc (const char c)
116{
117        S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
118
119        /* wait for room in the tx FIFO */
120        while (!(uart->UTRSTAT & 0x2));
121
122        uart->UTXH = c;
123
124        /* If \n, also do \r */
125        if (c == '\n')
126                rs485_putc ('\r');
127}
128
129/*
130 * Test whether a character is in the RX buffer
131 */
132int rs485_tstc (void)
133{
134        S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
135
136        return uart->UTRSTAT & 0x1;
137}
138
139void rs485_puts (const char *s)
140{
141        while (*s) {
142                rs485_putc (*s++);
143        }
144}
145
146
147/*
148 * State table:
149 *      RE      DE      Result
150 *      1       1       XMIT
151 *      0       0       RCV
152 *      1       0       Shutdown
153 */
154
155/* function that controls the receiver enable for the rs485 */
156/* rs485re_state reflects the level (0/1) of the RE pin */
157
158static void set_rs485re(unsigned char rs485re_state)
159{
160        if(rs485re_state)
161                *CPLD_RS485_RE = 0x010000;
162        else
163                *CPLD_RS485_RE = 0x0;
164}
165
166/* function that controls the sender enable for the rs485 */
167/* rs485de_state reflects the level (0/1) of the DE pin */
168
169static void set_rs485de(unsigned char rs485de_state)
170{
171        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
172
173        /* This is on PORT A bit 11 */
174        if(rs485de_state)
175                gpio->PADAT |= (1 << 11);
176        else
177                gpio->PADAT &= ~(1 << 11);
178}
179
180
181void trab_rs485_enable_tx(void)
182{
183        set_rs485de(1);
184        set_rs485re(1);
185}
186
187void trab_rs485_enable_rx(void)
188{
189        set_rs485re(0);
190        set_rs485de(0);
191}
192
193#ifdef  NOT_USED
194static void trab_rs485_disable_tx(void)
195{
196        set_rs485de(0);
197}
198
199static void trab_rs485_disable_rx(void)
200{
201        set_rs485re(1);
202}
203#endif
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