source: SVN/rincon/u-boot/board/xilinx/xilinx_enet/xemac_intr.c @ 55

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1/******************************************************************************
2*
3*     Author: Xilinx, Inc.
4*
5*
6*     This program is free software; you can redistribute it and/or modify it
7*     under the terms of the GNU General Public License as published by the
8*     Free Software Foundation; either version 2 of the License, or (at your
9*     option) any later version.
10*
11*
12*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
13*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
14*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
15*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
16*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
17*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
18*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
19*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
20*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
21*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
22*     FITNESS FOR A PARTICULAR PURPOSE.
23*
24*
25*     Xilinx hardware products are not intended for use in life support
26*     appliances, devices, or systems. Use in such applications is
27*     expressly prohibited.
28*
29*
30*     (c) Copyright 2002-2004 Xilinx Inc.
31*     All rights reserved.
32*
33*
34*     You should have received a copy of the GNU General Public License along
35*     with this program; if not, write to the Free Software Foundation, Inc.,
36*     675 Mass Ave, Cambridge, MA 02139, USA.
37*
38******************************************************************************/
39/*****************************************************************************/
40/**
41*
42* @file xemac_intr.c
43*
44* This file contains general interrupt-related functions of the XEmac driver.
45*
46* <pre>
47* MODIFICATION HISTORY:
48*
49* Ver   Who  Date     Changes
50* ----- ---- -------- -----------------------------------------------
51* 1.00a rpm  07/31/01 First release
52* 1.00b rpm  02/20/02 Repartitioned files and functions
53* 1.00c rpm  12/05/02 New version includes support for simple DMA
54* 1.00c rpm  03/31/03 Added comment to indicate that no Receive Length FIFO
55*                     overrun interrupts occur in v1.00l and later of the EMAC
56*                     device. This avoids the need to reset the device on
57*                     receive overruns.
58* </pre>
59*
60******************************************************************************/
61
62/***************************** Include Files *********************************/
63
64#include "xbasic_types.h"
65#include "xemac_i.h"
66#include "xio.h"
67#include "xipif_v1_23_b.h"      /* Uses v1.23b of the IPIF */
68
69/************************** Constant Definitions *****************************/
70
71/**************************** Type Definitions *******************************/
72
73/***************** Macros (Inline Functions) Definitions *********************/
74
75/************************** Variable Definitions *****************************/
76
77/************************** Function Prototypes ******************************/
78
79/*****************************************************************************/
80/**
81*
82* Set the callback function for handling asynchronous errors.  The upper layer
83* software should call this function during initialization.
84*
85* The error callback is invoked by the driver within interrupt context, so it
86* needs to do its job quickly. If there are potentially slow operations within
87* the callback, these should be done at task-level.
88*
89* The Xilinx errors that must be handled by the callback are:
90* - XST_DMA_ERROR indicates an unrecoverable DMA error occurred. This is
91*   typically a bus error or bus timeout. The handler must reset and
92*   re-configure the device.
93* - XST_FIFO_ERROR indicates an unrecoverable FIFO error occurred. This is a
94*   deadlock condition in the packet FIFO. The handler must reset and
95*   re-configure the device.
96* - XST_RESET_ERROR indicates an unrecoverable MAC error occurred, usually an
97*   overrun or underrun. The handler must reset and re-configure the device.
98* - XST_DMA_SG_NO_LIST indicates an attempt was made to access a scatter-gather
99*   DMA list that has not yet been created.
100* - XST_DMA_SG_LIST_EMPTY indicates the driver tried to get a descriptor from
101*   the receive descriptor list, but the list was empty.
102*
103* @param InstancePtr is a pointer to the XEmac instance to be worked on.
104* @param CallBackRef is a reference pointer to be passed back to the adapter in
105*        the callback. This helps the adapter correlate the callback to a
106*        particular driver.
107* @param FuncPtr is the pointer to the callback function.
108*
109* @return
110*
111* None.
112*
113* @note
114*
115* None.
116*
117******************************************************************************/
118void
119XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
120                      XEmac_ErrorHandler FuncPtr)
121{
122        XASSERT_VOID(InstancePtr != NULL);
123        XASSERT_VOID(FuncPtr != NULL);
124        XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
125
126        InstancePtr->ErrorHandler = FuncPtr;
127        InstancePtr->ErrorRef = CallBackRef;
128}
129
130/****************************************************************************/
131/*
132*
133* Check the interrupt status bits of the Ethernet MAC for errors. Errors
134* currently handled are:
135* - Receive length FIFO overrun. Indicates data was lost due to the receive
136*   length FIFO becoming full during the reception of a packet. Only a device
137*   reset clears this condition.
138* - Receive length FIFO underrun. An attempt to read an empty FIFO. Only a
139*   device reset clears this condition.
140* - Transmit status FIFO overrun. Indicates data was lost due to the transmit
141*   status FIFO becoming full following the transmission of a packet. Only a
142*   device reset clears this condition.
143* - Transmit status FIFO underrun. An attempt to read an empty FIFO. Only a
144*   device reset clears this condition.
145* - Transmit length FIFO overrun. Indicates data was lost due to the transmit
146*   length FIFO becoming full following the transmission of a packet. Only a
147*   device reset clears this condition.
148* - Transmit length FIFO underrun. An attempt to read an empty FIFO. Only a
149*   device reset clears this condition.
150* - Receive data FIFO overrun. Indicates data was lost due to the receive data
151*   FIFO becoming full during the reception of a packet.
152* - Receive data errors:
153*   - Receive missed frame error. Valid data was lost by the MAC.
154*   - Receive collision error. Data was lost by the MAC due to a collision.
155*   - Receive FCS error.  Data was dicarded by the MAC due to FCS error.
156*   - Receive length field error. Data was dicarded by the MAC due to an invalid
157*     length field in the packet.
158*   - Receive short error. Data was dicarded by the MAC because a packet was
159*     shorter than allowed.
160*   - Receive long error. Data was dicarded by the MAC because a packet was
161*     longer than allowed.
162*   - Receive alignment error. Data was truncated by the MAC because its length
163*     was not byte-aligned.
164*
165* @param InstancePtr is a pointer to the XEmac instance to be worked on.
166* @param IntrStatus is the contents of the interrupt status register to be checked
167*
168* @return
169*
170* None.
171*
172* @note
173*
174* This function is intended for internal use only.
175*
176******************************************************************************/
177void
178XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus)
179{
180        u32 ResetError = FALSE;
181
182        /*
183         * First check for receive fifo overrun/underrun errors. Most require a
184         * reset by the user to clear, but the data FIFO overrun error does not.
185         */
186        if (IntrStatus & XEM_EIR_RECV_DFIFO_OVER_MASK) {
187                InstancePtr->Stats.RecvOverrunErrors++;
188                InstancePtr->Stats.FifoErrors++;
189        }
190
191        if (IntrStatus & XEM_EIR_RECV_LFIFO_OVER_MASK) {
192                /*
193                 * Receive Length FIFO overrun interrupts no longer occur in v1.00l
194                 * and later of the EMAC device. Frames are just dropped by the EMAC
195                 * if the length FIFO is full. The user would notice the Receive Missed
196                 * Frame count incrementing without any other errors being reported.
197                 * This code is left here for backward compatibility with v1.00k and
198                 * older EMAC devices.
199                 */
200                InstancePtr->Stats.RecvOverrunErrors++;
201                InstancePtr->Stats.FifoErrors++;
202                ResetError = TRUE;      /* requires a reset */
203        }
204
205        if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
206                InstancePtr->Stats.RecvUnderrunErrors++;
207                InstancePtr->Stats.FifoErrors++;
208                ResetError = TRUE;      /* requires a reset */
209        }
210
211        /*
212         * Now check for general receive errors. Get the latest count where
213         * available, otherwise just bump the statistic so we know the interrupt
214         * occurred.
215         */
216        if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
217                if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
218                        /*
219                         * Caused by length FIFO or data FIFO overruns on receive side
220                         */
221                        InstancePtr->Stats.RecvMissedFrameErrors =
222                            XIo_In32(InstancePtr->BaseAddress +
223                                     XEM_RMFC_OFFSET);
224                }
225
226                if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
227                        InstancePtr->Stats.RecvCollisionErrors =
228                            XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
229                }
230
231                if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
232                        InstancePtr->Stats.RecvFcsErrors =
233                            XIo_In32(InstancePtr->BaseAddress +
234                                     XEM_RFCSEC_OFFSET);
235                }
236
237                if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
238                        InstancePtr->Stats.RecvLengthFieldErrors++;
239                }
240
241                if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
242                        InstancePtr->Stats.RecvShortErrors++;
243                }
244
245                if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
246                        InstancePtr->Stats.RecvLongErrors++;
247                }
248
249                if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
250                        InstancePtr->Stats.RecvAlignmentErrors =
251                            XIo_In32(InstancePtr->BaseAddress +
252                                     XEM_RAEC_OFFSET);
253                }
254
255                /*
256                 * Bump recv interrupts stats only if not scatter-gather DMA (this
257                 * stat gets bumped elsewhere in that case)
258                 */
259                if (!XEmac_mIsSgDma(InstancePtr)) {
260                        InstancePtr->Stats.RecvInterrupts++;    /* TODO: double bump? */
261                }
262
263        }
264
265        /*
266         * Check for transmit errors. These apply to both DMA and non-DMA modes
267         * of operation. The entire device should be reset after overruns or
268         * underruns.
269         */
270        if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
271                          XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
272                InstancePtr->Stats.XmitOverrunErrors++;
273                InstancePtr->Stats.FifoErrors++;
274                ResetError = TRUE;
275        }
276
277        if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
278                          XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
279                InstancePtr->Stats.XmitUnderrunErrors++;
280                InstancePtr->Stats.FifoErrors++;
281                ResetError = TRUE;
282        }
283
284        if (ResetError) {
285                /*
286                 * If a reset error occurred, disable the EMAC interrupts since the
287                 * reset-causing interrupt(s) is latched in the EMAC - meaning it will
288                 * keep occurring until the device is reset. In order to give the higher
289                 * layer software time to reset the device, we have to disable the
290                 * overrun/underrun interrupts until that happens. We trust that the
291                 * higher layer resets the device. We are able to get away with disabling
292                 * all EMAC interrupts since the only interrupts it generates are for
293                 * error conditions, and we don't care about any more errors right now.
294                 */
295                XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, 0);
296
297                /*
298                 * Invoke the error handler callback, which should result in a reset
299                 * of the device by the upper layer software.
300                 */
301                InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
302                                          XST_RESET_ERROR);
303        }
304}
305
306/*****************************************************************************/
307/*
308*
309* Check the receive packet FIFO for errors. FIFO error interrupts are:
310* - Deadlock.  See the XPacketFifo component for a description of deadlock on a
311*   FIFO.
312*
313* @param InstancePtr is a pointer to the XEmac instance to be worked on.
314*
315* @return
316*
317* Although the function returns void, it can return an asynchronous error to the
318* application through the error handler.  It can return XST_FIFO_ERROR if a FIFO
319* error occurred.
320*
321* @note
322*
323* This function is intended for internal use only.
324*
325******************************************************************************/
326void
327XEmac_CheckFifoRecvError(XEmac * InstancePtr)
328{
329        /*
330         * Although the deadlock is currently the only interrupt from a packet
331         * FIFO, make sure it is deadlocked before taking action. There is no
332         * need to clear this interrupt since it requires a reset of the device.
333         */
334        if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) {
335                u32 IntrEnable;
336
337                InstancePtr->Stats.FifoErrors++;
338
339                /*
340                 * Invoke the error callback function, which should result in a reset
341                 * of the device by the upper layer software. We first need to disable
342                 * the FIFO interrupt, since otherwise the upper layer thread that
343                 * handles the reset may never run because this interrupt condition
344                 * doesn't go away until a reset occurs (there is no way to ack it).
345                 */
346                IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
347                XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
348                                      IntrEnable & ~XEM_IPIF_RECV_FIFO_MASK);
349
350                InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
351                                          XST_FIFO_ERROR);
352        }
353}
354
355/*****************************************************************************/
356/*
357*
358* Check the send packet FIFO for errors. FIFO error interrupts are:
359* - Deadlock. See the XPacketFifo component for a description of deadlock on a
360*   FIFO.
361*
362* @param InstancePtr is a pointer to the XEmac instance to be worked on.
363*
364* @return
365*
366* Although the function returns void, it can return an asynchronous error to the
367* application through the error handler.  It can return XST_FIFO_ERROR if a FIFO
368* error occurred.
369*
370* @note
371*
372* This function is intended for internal use only.
373*
374******************************************************************************/
375void
376XEmac_CheckFifoSendError(XEmac * InstancePtr)
377{
378        /*
379         * Although the deadlock is currently the only interrupt from a packet
380         * FIFO, make sure it is deadlocked before taking action. There is no
381         * need to clear this interrupt since it requires a reset of the device.
382         */
383        if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) {
384                u32 IntrEnable;
385
386                InstancePtr->Stats.FifoErrors++;
387
388                /*
389                 * Invoke the error callback function, which should result in a reset
390                 * of the device by the upper layer software. We first need to disable
391                 * the FIFO interrupt, since otherwise the upper layer thread that
392                 * handles the reset may never run because this interrupt condition
393                 * doesn't go away until a reset occurs (there is no way to ack it).
394                 */
395                IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
396                XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
397                                      IntrEnable & ~XEM_IPIF_SEND_FIFO_MASK);
398
399                InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
400                                          XST_FIFO_ERROR);
401        }
402}
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