source: SVN/rincon/u-boot/board/xilinx/xilinx_iic/xiic_l.h @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

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Signed-off-by: Tim Harvey <tharvey@…>

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1/* $Id: xiic_l.h,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
2/*****************************************************************************
3*
4*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
5*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
6*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
7*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
8*       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
9*       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
10*       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
11*       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
12*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
13*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
14*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
15*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
16*       FOR A PARTICULAR PURPOSE.
17*
18*       (c) Copyright 2002 Xilinx Inc.
19*       All rights reserved.
20*
21*****************************************************************************/
22/****************************************************************************/
23/**
24*
25* @file xiic_l.h
26*
27* This header file contains identifiers and low-level driver functions (or
28* macros) that can be used to access the device.  High-level driver functions
29* are defined in xiic.h.
30*
31* <pre>
32* MODIFICATION HISTORY:
33*
34* Ver   Who  Date     Changes
35* ----- ---- -------- -----------------------------------------------
36* 1.00b jhl  05/07/02 First release
37* 1.01c ecm  12/05/02 new rev
38* </pre>
39*
40*****************************************************************************/
41
42#ifndef XIIC_L_H /* prevent circular inclusions */
43#define XIIC_L_H /* by using protection macros */
44
45/***************************** Include Files ********************************/
46
47#include "xbasic_types.h"
48
49/************************** Constant Definitions ****************************/
50
51#define XIIC_MSB_OFFSET                3
52
53#define XIIC_REG_OFFSET 0x100 + XIIC_MSB_OFFSET
54
55/*
56 * Register offsets in bytes from RegisterBase. Three is added to the
57 * base offset to access LSB (IBM style) of the word
58 */
59#define XIIC_CR_REG_OFFSET   0x00+XIIC_REG_OFFSET   /* Control Register   */
60#define XIIC_SR_REG_OFFSET   0x04+XIIC_REG_OFFSET   /* Status Register    */
61#define XIIC_DTR_REG_OFFSET  0x08+XIIC_REG_OFFSET   /* Data Tx Register   */
62#define XIIC_DRR_REG_OFFSET  0x0C+XIIC_REG_OFFSET   /* Data Rx Register   */
63#define XIIC_ADR_REG_OFFSET  0x10+XIIC_REG_OFFSET   /* Address Register   */
64#define XIIC_TFO_REG_OFFSET  0x14+XIIC_REG_OFFSET   /* Tx FIFO Occupancy  */
65#define XIIC_RFO_REG_OFFSET  0x18+XIIC_REG_OFFSET   /* Rx FIFO Occupancy  */
66#define XIIC_TBA_REG_OFFSET  0x1C+XIIC_REG_OFFSET   /* 10 Bit Address reg */
67#define XIIC_RFD_REG_OFFSET  0x20+XIIC_REG_OFFSET   /* Rx FIFO Depth reg  */
68
69/* Control Register masks */
70
71#define XIIC_CR_ENABLE_DEVICE_MASK        0x01  /* Device enable = 1      */
72#define XIIC_CR_TX_FIFO_RESET_MASK        0x02  /* Transmit FIFO reset=1  */
73#define XIIC_CR_MSMS_MASK                 0x04  /* Master starts Txing=1  */
74#define XIIC_CR_DIR_IS_TX_MASK            0x08  /* Dir of tx. Txing=1     */
75#define XIIC_CR_NO_ACK_MASK               0x10  /* Tx Ack. NO ack = 1     */
76#define XIIC_CR_REPEATED_START_MASK       0x20  /* Repeated start = 1     */
77#define XIIC_CR_GENERAL_CALL_MASK         0x40  /* Gen Call enabled = 1   */
78
79/* Status Register masks */
80
81#define XIIC_SR_GEN_CALL_MASK             0x01  /* 1=a mstr issued a GC   */
82#define XIIC_SR_ADDR_AS_SLAVE_MASK        0x02  /* 1=when addr as slave   */
83#define XIIC_SR_BUS_BUSY_MASK             0x04  /* 1 = bus is busy        */
84#define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08  /* 1=Dir: mstr <-- slave  */
85#define XIIC_SR_TX_FIFO_FULL_MASK         0x10  /* 1 = Tx FIFO full       */
86#define XIIC_SR_RX_FIFO_FULL_MASK         0x20  /* 1 = Rx FIFO full       */
87#define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40  /* 1 = Rx FIFO empty      */
88
89/* IPIF Interrupt Status Register masks    Interrupt occurs when...       */
90
91#define XIIC_INTR_ARB_LOST_MASK           0x01  /* 1 = arbitration lost   */
92#define XIIC_INTR_TX_ERROR_MASK           0x02  /* 1=Tx error/msg complete*/
93#define XIIC_INTR_TX_EMPTY_MASK           0x04  /* 1 = Tx FIFO/reg empty  */
94#define XIIC_INTR_RX_FULL_MASK            0x08  /* 1=Rx FIFO/reg=OCY level*/
95#define XIIC_INTR_BNB_MASK                0x10  /* 1 = Bus not busy       */
96#define XIIC_INTR_AAS_MASK                0x20  /* 1 = when addr as slave */
97#define XIIC_INTR_NAAS_MASK               0x40  /* 1 = not addr as slave  */
98#define XIIC_INTR_TX_HALF_MASK            0x80  /* 1 = TX FIFO half empty */
99
100/* IPIF Device Interrupt Register masks */
101
102#define XIIC_IPIF_IIC_MASK          0x00000004UL    /* 1=inter enabled */
103#define XIIC_IPIF_ERROR_MASK        0x00000001UL    /* 1=inter enabled */
104#define XIIC_IPIF_INTER_ENABLE_MASK  (XIIC_IPIF_IIC_MASK |  \
105                                      XIIC_IPIF_ERROR_MASK)
106
107#define XIIC_TX_ADDR_SENT             0x00
108#define XIIC_TX_ADDR_MSTR_RECV_MASK   0x02
109
110/* The following constants specify the depth of the FIFOs */
111
112#define IIC_RX_FIFO_DEPTH         16   /* Rx fifo capacity               */
113#define IIC_TX_FIFO_DEPTH         16   /* Tx fifo capacity               */
114
115/* The following constants specify groups of interrupts that are typically
116 * enabled or disables at the same time
117 */
118#define XIIC_TX_INTERRUPTS                                          \
119            (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK |    \
120             XIIC_INTR_TX_HALF_MASK)
121
122#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
123
124/* The following constants are used with the following macros to specify the
125 * operation, a read or write operation.
126 */
127#define XIIC_READ_OPERATION  1
128#define XIIC_WRITE_OPERATION 0
129
130/* The following constants are used with the transmit FIFO fill function to
131 * specify the role which the IIC device is acting as, a master or a slave.
132 */
133#define XIIC_MASTER_ROLE     1
134#define XIIC_SLAVE_ROLE      0
135
136/**************************** Type Definitions ******************************/
137
138
139/***************** Macros (Inline Functions) Definitions ********************/
140
141
142/************************** Function Prototypes *****************************/
143
144unsigned XIic_Recv(u32 BaseAddress, u8 Address,
145                   u8 *BufferPtr, unsigned ByteCount);
146
147unsigned XIic_Send(u32 BaseAddress, u8 Address,
148                   u8 *BufferPtr, unsigned ByteCount);
149
150#endif            /* end of protection macro */
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