source: SVN/rincon/u-boot/board/xpedite1k/init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.0 KB
Line 
1/*
2*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
3*
4* See file CREDITS for list of people who contributed to this
5* project.
6*
7* This program is free software; you can redistribute it and/or
8* modify it under the terms of the GNU General Public License as
9* published by the Free Software Foundation; either version 2 of
10* the License, or (at your option) any later version.
11*
12* This program is distributed in the hope that it will be useful,
13* but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.   See the
15* GNU General Public License for more details.
16*
17* You should have received a copy of the GNU General Public License
18* along with this program; if not, write to the Free Software
19* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20* MA 02111-1307 USA
21*/
22
23#include <ppc_asm.tmpl>
24#include <config.h>
25
26/* General */
27#define TLB_VALID   0x00000200
28
29/* Supported page sizes */
30
31#define SZ_1K       0x00000000
32#define SZ_4K       0x00000010
33#define SZ_16K      0x00000020
34#define SZ_64K      0x00000030
35#define SZ_256K     0x00000040
36#define SZ_1M       0x00000050
37#define SZ_16M      0x00000070
38#define SZ_256M     0x00000090
39
40/* Storage attributes */
41#define SA_W        0x00000800      /* Write-through */
42#define SA_I        0x00000400      /* Caching inhibited */
43#define SA_M        0x00000200      /* Memory coherence */
44#define SA_G        0x00000100      /* Guarded */
45#define SA_E        0x00000080      /* Endian */
46
47/* Access control */
48#define AC_X        0x00000024      /* Execute */
49#define AC_W        0x00000012      /* Write */
50#define AC_R        0x00000009      /* Read */
51
52/* Some handy macros */
53
54#define EPN(e)          ((e) & 0xfffffc00)
55#define TLB0(epn,sz)    ( (EPN((epn)) | (sz) | TLB_VALID ) )
56#define TLB1(rpn,erpn)  ( ((rpn)&0xfffffc00) | (erpn) )
57#define TLB2(a)         ( (a)&0x00000fbf )
58
59#define tlbtab_start\
60        mflr    r1  ;\
61        bl 0f       ;
62
63#define tlbtab_end\
64        .long 0, 0, 0   ;   \
650:      mflr    r0      ;   \
66        mtlr    r1      ;   \
67        blr             ;
68
69#define tlbentry(epn,sz,rpn,erpn,attr)\
70        .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
71
72
73/**************************************************************************
74 * TLB TABLE
75 *
76 * This table is used by the cpu boot code to setup the initial tlb
77 * entries. Rather than make broad assumptions in the cpu source tree,
78 * this table lets each board set things up however they like.
79 *
80 *  Pointer to the table is returned in r1
81 *
82 *************************************************************************/
83
84        .section .bootpg,"ax"
85        .globl tlbtab
86
87tlbtab:
88        tlbtab_start
89        tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
90        tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
91        tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
92        tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
93        tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
94        tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
95        tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
96        tlbtab_end
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