source: SVN/rincon/u-boot/cpu/arm1176/s3c64xx/cpu_init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 23 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.2 KB
Line 
1/*
2 * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
3 *
4 * Copyright (C) 2008
5 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <s3c6400.h>
28
29        .globl mem_ctrl_asm_init
30mem_ctrl_asm_init:
31        /* Memory subsystem address 0x7e00f120 */
32        ldr     r0, =ELFIN_MEM_SYS_CFG
33
34        /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
35        mov     r1, #0xd
36        str     r1, [r0]
37
38        /* DMC1 base address 0x7e001000 */
39        ldr     r0, =ELFIN_DMC1_BASE
40
41        ldr     r1, =0x4
42        str     r1, [r0, #INDEX_DMC_MEMC_CMD]
43
44        ldr     r1, =DMC_DDR_REFRESH_PRD
45        str     r1, [r0, #INDEX_DMC_REFRESH_PRD]
46
47        ldr     r1, =DMC_DDR_CAS_LATENCY
48        str     r1, [r0, #INDEX_DMC_CAS_LATENCY]
49
50        ldr     r1, =DMC_DDR_t_DQSS
51        str     r1, [r0, #INDEX_DMC_T_DQSS]
52
53        ldr     r1, =DMC_DDR_t_MRD
54        str     r1, [r0, #INDEX_DMC_T_MRD]
55
56        ldr     r1, =DMC_DDR_t_RAS
57        str     r1, [r0, #INDEX_DMC_T_RAS]
58
59        ldr     r1, =DMC_DDR_t_RC
60        str     r1, [r0, #INDEX_DMC_T_RC]
61
62        ldr     r1, =DMC_DDR_t_RCD
63        ldr     r2, =DMC_DDR_schedule_RCD
64        orr     r1, r1, r2
65        str     r1, [r0, #INDEX_DMC_T_RCD]
66
67        ldr     r1, =DMC_DDR_t_RFC
68        ldr     r2, =DMC_DDR_schedule_RFC
69        orr     r1, r1, r2
70        str     r1, [r0, #INDEX_DMC_T_RFC]
71
72        ldr     r1, =DMC_DDR_t_RP
73        ldr     r2, =DMC_DDR_schedule_RP
74        orr     r1, r1, r2
75        str     r1, [r0, #INDEX_DMC_T_RP]
76
77        ldr     r1, =DMC_DDR_t_RRD
78        str     r1, [r0, #INDEX_DMC_T_RRD]
79
80        ldr     r1, =DMC_DDR_t_WR
81        str     r1, [r0, #INDEX_DMC_T_WR]
82
83        ldr     r1, =DMC_DDR_t_WTR
84        str     r1, [r0, #INDEX_DMC_T_WTR]
85
86        ldr     r1, =DMC_DDR_t_XP
87        str     r1, [r0, #INDEX_DMC_T_XP]
88
89        ldr     r1, =DMC_DDR_t_XSR
90        str     r1, [r0, #INDEX_DMC_T_XSR]
91
92        ldr     r1, =DMC_DDR_t_ESR
93        str     r1, [r0, #INDEX_DMC_T_ESR]
94
95        ldr     r1, =DMC1_MEM_CFG
96        str     r1, [r0, #INDEX_DMC_MEMORY_CFG]
97
98        ldr     r1, =DMC1_MEM_CFG2
99        str     r1, [r0, #INDEX_DMC_MEMORY_CFG2]
100
101        ldr     r1, =DMC1_CHIP0_CFG
102        str     r1, [r0, #INDEX_DMC_CHIP_0_CFG]
103
104        ldr     r1, =DMC_DDR_32_CFG
105        str     r1, [r0, #INDEX_DMC_USER_CONFIG]
106
107        /* DMC0 DDR Chip 0 configuration direct command reg */
108        ldr     r1, =DMC_NOP0
109        str     r1, [r0, #INDEX_DMC_DIRECT_CMD]
110
111        /* Precharge All */
112        ldr     r1, =DMC_PA0
113        str     r1, [r0, #INDEX_DMC_DIRECT_CMD]
114
115        /* Auto Refresh 2 time */
116        ldr     r1, =DMC_AR0
117        str     r1, [r0, #INDEX_DMC_DIRECT_CMD]
118        str     r1, [r0, #INDEX_DMC_DIRECT_CMD]
119
120        /* MRS */
121        ldr     r1, =DMC_mDDR_EMR0
122        str     r1, [r0, #INDEX_DMC_DIRECT_CMD]
123
124        /* Mode Reg */
125        ldr     r1, =DMC_mDDR_MR0
126        str     r1, [r0, #INDEX_DMC_DIRECT_CMD]
127
128        /* Enable DMC1 */
129        mov     r1, #0x0
130        str     r1, [r0, #INDEX_DMC_MEMC_CMD]
131
132check_dmc1_ready:
133        ldr     r1, [r0, #INDEX_DMC_MEMC_STATUS]
134        mov     r2, #0x3
135        and     r1, r1, r2
136        cmp     r1, #0x1
137        bne     check_dmc1_ready
138        nop
139
140        mov     pc, lr
141
142        .ltorg
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