source: SVN/rincon/u-boot/cpu/arm926ejs/davinci/reset.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 1.6 KB
Line 
1/*
2 * Processor reset using WDT for TI TMS320DM644x SoC.
3 *
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 *
6 * -----------------------------------------------------
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24.globl reset_cpu
25reset_cpu:
26        ldr     r0, WDT_TGCR
27        mov     r1, $0x08
28        str     r1, [r0]
29        ldr     r1, [r0]
30        orr     r1, r1, $0x03
31        str     r1, [r0]
32        mov     r1, $0
33        ldr     r0, WDT_TIM12
34        str     r1, [r0]
35        ldr     r0, WDT_TIM34
36        str     r1, [r0]
37        ldr     r0, WDT_PRD12
38        str     r1, [r0]
39        ldr     r0, WDT_PRD34
40        str     r1, [r0]
41        ldr     r0, WDT_TCR
42        ldr     r1, [r0]
43        orr     r1, r1, $0x40
44        str     r1, [r0]
45        ldr     r0, WDT_WDTCR
46        ldr     r1, [r0]
47        orr     r1, r1, $0x4000
48        str     r1, [r0]
49        ldr     r1, WDTCR_VAL1
50        str     r1, [r0]
51        ldr     r1, WDTCR_VAL2
52        str     r1, [r0]
53        nop
54        nop
55        nop
56        nop
57reset_cpu_loop:
58        b       reset_cpu_loop
59
60WDT_TGCR:
61        .word   0x01c21c24
62WDT_TIM12:
63        .word   0x01c21c10
64WDT_TIM34:
65        .word   0x01c21c14
66WDT_PRD12:
67        .word   0x01c21c18
68WDT_PRD34:
69        .word   0x01c21c1c
70WDT_TCR:
71        .word   0x01c21c20
72WDT_WDTCR:
73        .word   0x01c21c28
74WDTCR_VAL1:
75        .word   0xa5c64000
76WDTCR_VAL2:
77        .word   0xda7e4000
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