source: SVN/rincon/u-boot/cpu/arm926ejs/start.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

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Signed-off-by: Tim Harvey <tharvey@…>

File size: 10.1 KB
Line 
1/*
2 *  armboot - Startup Code for ARM926EJS CPU-core
3 *
4 *  Copyright (c) 2003  Texas Instruments
5 *
6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
9 *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
10 *  Copyright (c) 2002  Gary Jennejohn <gj@denx.de>
11 *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
12 *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33
34#include <config.h>
35#include <version.h>
36
37#if defined(CONFIG_OMAP1610)
38#include <./configs/omap1510.h>
39#elif defined(CONFIG_OMAP730)
40#include <./configs/omap730.h>
41#endif
42
43/*
44 *************************************************************************
45 *
46 * Jump vector table as in table 3.1 in [1]
47 *
48 *************************************************************************
49 */
50
51
52.globl _start
53_start:
54        b       reset
55        ldr     pc, _undefined_instruction
56        ldr     pc, _software_interrupt
57        ldr     pc, _prefetch_abort
58        ldr     pc, _data_abort
59        ldr     pc, _not_used
60        ldr     pc, _irq
61        ldr     pc, _fiq
62
63_undefined_instruction:
64        .word undefined_instruction
65_software_interrupt:
66        .word software_interrupt
67_prefetch_abort:
68        .word prefetch_abort
69_data_abort:
70        .word data_abort
71_not_used:
72        .word not_used
73_irq:
74        .word irq
75_fiq:
76        .word fiq
77
78        .balignl 16,0xdeadbeef
79
80
81/*
82 *************************************************************************
83 *
84 * Startup Code (reset vector)
85 *
86 * do important init only if we don't start from memory!
87 * setup Memory and board specific bits prior to relocation.
88 * relocate armboot to ram
89 * setup stack
90 *
91 *************************************************************************
92 */
93
94_TEXT_BASE:
95        .word   TEXT_BASE
96
97.globl _armboot_start
98_armboot_start:
99        .word _start
100
101/*
102 * These are defined in the board-specific linker script.
103 */
104.globl _bss_start
105_bss_start:
106        .word __bss_start
107
108.globl _bss_end
109_bss_end:
110        .word _end
111
112#ifdef CONFIG_USE_IRQ
113/* IRQ stack memory (calculated at run-time) */
114.globl IRQ_STACK_START
115IRQ_STACK_START:
116        .word   0x0badc0de
117
118/* IRQ stack memory (calculated at run-time) */
119.globl FIQ_STACK_START
120FIQ_STACK_START:
121        .word 0x0badc0de
122#endif
123
124
125/*
126 * the actual reset code
127 */
128
129EMAC_CTRL:
130        .word 0x01c41a14
131
132EMAC_STAT:
133        .word 0x01c41814
134
135EMAC_CTRL2:
136        .word 0x01c41a18
137
138EMAC_STAT2:
139        .word 0x01c41818
140
141PSCTRL:
142        .word 0x01c41120
143
144PSCSTAT:
145        .word 0x01c41128
146
147VDD3P3V_PWDN:
148        .word 0x01c40048
149
150PINMUX0:
151        .word 0x01c40000
152
153PINMUX0_VAL:
154        .word 0x80000c1f
155
156reset:
157        /*
158         * set the cpu to SVC32 mode
159         */
160        mrs     r0,cpsr
161        bic     r0,r0,#0x1f
162        orr     r0,r0,#0xd3
163        msr     cpsr,r0
164
165        // Enable EMAC
166        ldr r6, EMAC_CTRL
167        ldr r7, [r6]
168        orr r7, r7, #0x3
169        orr r7, r7, #0x200
170        str r7, [r6]
171
172  ldr r6, PSCTRL
173  ldr r7, [r6]
174  orr r7, r7, $0x01
175  str r7, [r6]
176
177checkStatClkEnEMAC:
178  ldr r6, PSCSTAT
179  ldr r7, [r6]
180  ands  r7, r7, $0x01
181  bne checkStatClkEnEMAC
182
183checkEMACStatClkEn:
184  ldr r6, EMAC_STAT
185  ldr r7, [r6]
186  and r7, r7, $0x1f
187  cmp r7, $0x03
188  bne checkEMACStatClkEn
189
190
191        // Enable EMAC Wrapper
192        ldr r6, EMAC_CTRL2
193        ldr r7, [r6]
194        orr r7, r7, #0x3
195        orr r7, r7, #0x200
196        str r7, [r6]
197
198  ldr r6, PSCTRL
199  ldr r7, [r6]
200  orr r7, r7, $0x01
201  str r7, [r6]
202
203checkStatClkEnEMAC2:
204  ldr r6, PSCSTAT
205  ldr r7, [r6]
206  ands  r7, r7, $0x01
207  bne checkStatClkEnEMAC2
208
209checkEMACStatClkEn2:
210  ldr r6, EMAC_STAT2
211  ldr r7, [r6]
212  and r7, r7, $0x1f
213  cmp r7, $0x03
214  bne checkEMACStatClkEn2
215
216       
217        // VDD3P3v_pwdn
218        ldr r6, VDD3P3V_PWDN
219        mov r7, #0
220        str r7, [r6]
221
222        // PinMux0
223        ldr r6, PINMUX0
224        ldr r7, PINMUX0_VAL
225        str r7, [r6]
226
227        /*
228         * we do sys-critical inits only at reboot,
229         * not when booting from ram!
230         */
231#ifndef CONFIG_SKIP_LOWLEVEL_INIT
232        bl      cpu_init_crit
233#endif
234
235#ifndef CONFIG_SKIP_RELOCATE_UBOOT
236relocate:                               /* relocate U-Boot to RAM           */
237        adr     r0, _start              /* r0 <- current position of code   */
238        ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
239        cmp     r0, r1                  /* don't reloc during debug         */
240        beq     stack_setup
241
242        ldr     r2, _armboot_start
243        ldr     r3, _bss_start
244        sub     r2, r3, r2              /* r2 <- size of armboot            */
245        add     r2, r0, r2              /* r2 <- source end address         */
246
247copy_loop:
248        ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
249        stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
250        cmp     r0, r2                  /* until source end addreee [r2]    */
251        ble     copy_loop
252#endif  /* CONFIG_SKIP_RELOCATE_UBOOT */
253
254        /* Set up the stack                                                 */
255stack_setup:
256        ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
257        sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
258        sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
259#ifdef CONFIG_USE_IRQ
260        sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
261#endif
262        sub     sp, r0, #12             /* leave 3 words for abort-stack    */
263
264clear_bss:
265        ldr     r0, _bss_start          /* find start of bss segment        */
266        ldr     r1, _bss_end            /* stop here                        */
267        mov     r2, #0x00000000         /* clear                            */
268
269clbss_l:str     r2, [r0]                /* clear loop...                    */
270        add     r0, r0, #4
271        cmp     r0, r1
272        ble     clbss_l
273
274        bl coloured_LED_init
275        bl red_LED_on
276
277        ldr     pc, _start_armboot
278
279_start_armboot:
280        .word start_armboot
281
282
283/*
284 *************************************************************************
285 *
286 * CPU_init_critical registers
287 *
288 * setup important registers
289 * setup memory timing
290 *
291 *************************************************************************
292 */
293#ifndef CONFIG_SKIP_LOWLEVEL_INIT
294cpu_init_crit:
295        /*
296         * flush v4 I/D caches
297         */
298        mov     r0, #0
299        mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
300        mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
301
302        /*
303         * disable MMU stuff and caches
304         */
305        mrc     p15, 0, r0, c1, c0, 0
306        bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
307        bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
308        orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
309        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
310        mcr     p15, 0, r0, c1, c0, 0
311
312        /*
313         * Go setup Memory and board specific bits prior to relocation.
314         */
315        mov     ip, lr          /* perserve link reg across call */
316        bl      lowlevel_init   /* go setup pll,mux,memory */
317        mov     lr, ip          /* restore link */
318        mov     pc, lr          /* back to my caller */
319#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
320
321/*
322 *************************************************************************
323 *
324 * Interrupt handling
325 *
326 *************************************************************************
327 */
328
329@
330@ IRQ stack frame.
331@
332#define S_FRAME_SIZE    72
333
334#define S_OLD_R0        68
335#define S_PSR           64
336#define S_PC            60
337#define S_LR            56
338#define S_SP            52
339
340#define S_IP            48
341#define S_FP            44
342#define S_R10           40
343#define S_R9            36
344#define S_R8            32
345#define S_R7            28
346#define S_R6            24
347#define S_R5            20
348#define S_R4            16
349#define S_R3            12
350#define S_R2            8
351#define S_R1            4
352#define S_R0            0
353
354#define MODE_SVC 0x13
355#define I_BIT    0x80
356
357/*
358 * use bad_save_user_regs for abort/prefetch/undef/swi ...
359 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
360 */
361
362        .macro  bad_save_user_regs
363        @ carve out a frame on current user stack
364        sub     sp, sp, #S_FRAME_SIZE
365        stmia   sp, {r0 - r12}  @ Save user registers (now in svc mode) r0-r12
366
367        ldr     r2, _armboot_start
368        sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
369        sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
370        @ get values for "aborted" pc and cpsr (into parm regs)
371        ldmia   r2, {r2 - r3}
372        add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
373        add     r5, sp, #S_SP
374        mov     r1, lr
375        stmia   r5, {r0 - r3}   @ save sp_SVC, lr_SVC, pc, cpsr
376        mov     r0, sp          @ save current stack into r0 (param register)
377        .endm
378
379        .macro  irq_save_user_regs
380        sub     sp, sp, #S_FRAME_SIZE
381        stmia   sp, {r0 - r12}                  @ Calling r0-r12
382        @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
383        add     r8, sp, #S_PC
384        stmdb   r8, {sp, lr}^           @ Calling SP, LR
385        str     lr, [r8, #0]            @ Save calling PC
386        mrs     r6, spsr
387        str     r6, [r8, #4]            @ Save CPSR
388        str     r0, [r8, #8]            @ Save OLD_R0
389        mov     r0, sp
390        .endm
391
392        .macro  irq_restore_user_regs
393        ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
394        mov     r0, r0
395        ldr     lr, [sp, #S_PC]                 @ Get PC
396        add     sp, sp, #S_FRAME_SIZE
397        subs    pc, lr, #4              @ return & move spsr_svc into cpsr
398        .endm
399
400        .macro get_bad_stack
401        ldr     r13, _armboot_start             @ setup our mode stack
402        sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
403        sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
404
405        str     lr, [r13]       @ save caller lr in position 0 of saved stack
406        mrs     lr, spsr        @ get the spsr
407        str     lr, [r13, #4]   @ save spsr in position 1 of saved stack
408        mov     r13, #MODE_SVC  @ prepare SVC-Mode
409        @ msr   spsr_c, r13
410        msr     spsr, r13       @ switch modes, make sure moves will execute
411        mov     lr, pc          @ capture return pc
412        movs    pc, lr          @ jump to next instruction & switch modes.
413        .endm
414
415        .macro get_irq_stack                    @ setup IRQ stack
416        ldr     sp, IRQ_STACK_START
417        .endm
418
419        .macro get_fiq_stack                    @ setup FIQ stack
420        ldr     sp, FIQ_STACK_START
421        .endm
422
423/*
424 * exception handlers
425 */
426        .align  5
427undefined_instruction:
428        get_bad_stack
429        bad_save_user_regs
430        bl      do_undefined_instruction
431
432        .align  5
433software_interrupt:
434        get_bad_stack
435        bad_save_user_regs
436        bl      do_software_interrupt
437
438        .align  5
439prefetch_abort:
440        get_bad_stack
441        bad_save_user_regs
442        bl      do_prefetch_abort
443
444        .align  5
445data_abort:
446        get_bad_stack
447        bad_save_user_regs
448        bl      do_data_abort
449
450        .align  5
451not_used:
452        get_bad_stack
453        bad_save_user_regs
454        bl      do_not_used
455
456#ifdef CONFIG_USE_IRQ
457
458        .align  5
459irq:
460        get_irq_stack
461        irq_save_user_regs
462        bl      do_irq
463        irq_restore_user_regs
464
465        .align  5
466fiq:
467        get_fiq_stack
468        /* someone ought to write a more effiction fiq_save_user_regs */
469        irq_save_user_regs
470        bl      do_fiq
471        irq_restore_user_regs
472
473#else
474
475        .align  5
476irq:
477        get_bad_stack
478        bad_save_user_regs
479        bl      do_irq
480
481        .align  5
482fiq:
483        get_bad_stack
484        bad_save_user_regs
485        bl      do_fiq
486
487#endif
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