source: SVN/rincon/u-boot/cpu/at32ap/at32ap700x/clk.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 3 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 2.0 KB
Line 
1/*
2 * Copyright (C) 2005-2008 Atmel Corporation
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22#include <common.h>
23
24#include <asm/io.h>
25
26#include <asm/arch/clk.h>
27#include <asm/arch/memory-map.h>
28
29#include "sm.h"
30
31void clk_init(void)
32{
33        uint32_t cksel;
34
35        /* in case of soft resets, disable watchdog */
36        sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
37        sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
38
39#ifdef CONFIG_PLL
40        /* Initialize the PLL */
41        sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
42                            | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
43                            | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
44                            | SM_BF(PLLOPT, CFG_PLL0_OPT)
45                            | SM_BF(PLLOSC, 0)
46                            | SM_BIT(PLLEN)));
47
48        /* Wait for lock */
49        while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
50#endif
51
52        /* Set up clocks for the CPU and all peripheral buses */
53        cksel = 0;
54        if (CFG_CLKDIV_CPU)
55                cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
56        if (CFG_CLKDIV_HSB)
57                cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
58        if (CFG_CLKDIV_PBA)
59                cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
60        if (CFG_CLKDIV_PBB)
61                cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
62        sm_writel(PM_CKSEL, cksel);
63
64#ifdef CONFIG_PLL
65        /* Use PLL0 as main clock */
66        sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
67#endif
68}
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