source: SVN/rincon/u-boot/cpu/at32ap/cpu.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 2.5 KB
Line 
1/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22#include <common.h>
23#include <command.h>
24
25#include <asm/io.h>
26#include <asm/sections.h>
27#include <asm/sysreg.h>
28
29#include <asm/arch/clk.h>
30#include <asm/arch/memory-map.h>
31
32#include "hsmc3.h"
33
34/* Sanity checks */
35#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB)           \
36        || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA)    \
37        || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
38# error Constraint fCPU >= fHSB >= fPB{A,B} violated
39#endif
40#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
41# error Invalid PLL multiplier and/or divider
42#endif
43
44DECLARE_GLOBAL_DATA_PTR;
45
46int cpu_init(void)
47{
48        extern void _evba(void);
49
50        gd->cpu_hz = CFG_OSC0_HZ;
51
52        /* TODO: Move somewhere else, but needs to be run before we
53         * increase the clock frequency. */
54        hsmc3_writel(MODE0, 0x00031103);
55        hsmc3_writel(CYCLE0, 0x000c000d);
56        hsmc3_writel(PULSE0, 0x0b0a0906);
57        hsmc3_writel(SETUP0, 0x00010002);
58
59        clk_init();
60
61        /* Update the CPU speed according to the PLL configuration */
62        gd->cpu_hz = get_cpu_clk_rate();
63
64        /* Set up the exception handler table and enable exceptions */
65        sysreg_write(EVBA, (unsigned long)&_evba);
66        asm volatile("csrf      %0" : : "i"(SYSREG_EM_OFFSET));
67
68        if(gclk_init)
69                gclk_init();
70
71        return 0;
72}
73
74void prepare_to_boot(void)
75{
76        /* Flush both caches and the write buffer */
77        asm volatile("cache  %0[4], 010\n\t"
78                     "cache  %0[0], 000\n\t"
79                     "sync   0" : : "r"(0) : "memory");
80}
81
82int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
83{
84        /* This will reset the CPU core, caches, MMU and all internal busses */
85        __builtin_mtdr(8, 1 << 13);     /* set DC:DBE */
86        __builtin_mtdr(8, 1 << 30);     /* set DC:RES */
87
88        /* Flush the pipeline before we declare it a failure */
89        asm volatile("sub   pc, pc, -4");
90
91        return -1;
92}
Note: See TracBrowser for help on using the repository browser.