source: SVN/rincon/u-boot/cpu/blackfin/cache.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 1.0 KB
Line 
1/* cache.S - low level cache handling routines
2 * Copyright (C) 2003-2007 Analog Devices Inc.
3 * Licensed under the GPL-2 or later.
4 */
5
6#include <asm/linkage.h>
7#include <config.h>
8#include <asm/blackfin.h>
9
10.text
11.align 2
12ENTRY(_blackfin_icache_flush_range)
13        R2 = -32;
14        R2 = R0 & R2;
15        P0 = R2;
16        P1 = R1;
17        CSYNC;
181:
19        IFLUSH[P0++];
20        CC = P0 < P1(iu);
21        IF CC JUMP 1b(bp);
22        IFLUSH[P0];
23        SSYNC;
24        RTS;
25ENDPROC(_blackfin_icache_flush_range)
26
27ENTRY(_blackfin_dcache_flush_range)
28        R2 = -32;
29        R2 = R0 & R2;
30        P0 = R2;
31        P1 = R1;
32        CSYNC;
331:
34        FLUSH[P0++];
35        CC = P0 < P1(iu);
36        IF CC JUMP 1b(bp);
37        FLUSH[P0];
38        SSYNC;
39        RTS;
40ENDPROC(_blackfin_dcache_flush_range)
41
42ENTRY(_blackfin_dcache_invalidate_range)
43        R2 = -32;
44        R2 = R0 & R2;
45        P0 = R2;
46        P1 = R1;
47        CSYNC;
481:
49        FLUSHINV[P0++];
50        CC = P0 < P1(iu);
51        IF CC JUMP 1b(bp);
52
53        /*
54         * If the data crosses a cache line, then we'll be pointing to
55         * the last cache line, but won't have flushed/invalidated it yet, so do
56         * one more.
57         */
58        FLUSHINV[P0];
59        SSYNC;
60        RTS;
61ENDPROC(_blackfin_dcache_invalidate_range)
Note: See TracBrowser for help on using the repository browser.