source: SVN/rincon/u-boot/cpu/blackfin/initcode.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 9.8 KB
Line 
1/*
2 * initcode.c - Initialize the processor.  This is usually entails things
3 * like external memory, voltage regulators, etc...  Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
6 *
7 * Copyright (c) 2004-2008 Analog Devices Inc.
8 *
9 * Licensed under the GPL-2 or later.
10 */
11
12#include <config.h>
13#include <asm/blackfin.h>
14#include <asm/mach-common/bits/bootrom.h>
15#include <asm/mach-common/bits/ebiu.h>
16#include <asm/mach-common/bits/pll.h>
17#include <asm/mach-common/bits/uart.h>
18
19#define BFIN_IN_INITCODE
20#include "serial.h"
21
22__attribute__((always_inline))
23static inline uint32_t serial_init(void)
24{
25#ifdef __ADSPBF54x__
26# ifdef BFIN_BOOT_UART_USE_RTS
27#  define BFIN_UART_USE_RTS 1
28# else
29#  define BFIN_UART_USE_RTS 0
30# endif
31        if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
32                size_t i;
33
34                /* force RTS rather than relying on auto RTS */
35                bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL);
36
37                /* Wait for the line to clear up.  We cannot rely on UART
38                 * registers as none of them reflect the status of the RSR.
39                 * Instead, we'll sleep for ~10 bit times at 9600 baud.
40                 * We can precalc things here by assuming boot values for
41                 * PLL rather than loading registers and calculating.
42                 *      baud    = SCLK / (16 ^ (1 - EDBO) * Divisor)
43                 *      EDB0    = 0
44                 *      Divisor = (SCLK / baud) / 16
45                 *      SCLK    = baud * 16 * Divisor
46                 *      SCLK    = (0x14 * CONFIG_CLKIN_HZ) / 5
47                 *      CCLK    = (16 * Divisor * 5) * (9600 / 10)
48                 * In reality, this will probably be just about 1 second delay,
49                 * so assuming 9600 baud is OK (both as a very low and too high
50                 * speed as this will buffer things enough).
51                 */
52#define _NUMBITS (10)                                   /* how many bits to delay */
53#define _LOWBAUD (9600)                                 /* low baud rate */
54#define _SCLK    ((0x14 * CONFIG_CLKIN_HZ) / 5)         /* SCLK based on PLL */
55#define _DIVISOR ((_SCLK / _LOWBAUD) / 16)              /* UART DLL/DLH */
56#define _NUMINS  (3)                                    /* how many instructions in loop */
57#define _CCLK    (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
58                i = _CCLK;
59                while (i--)
60                        asm volatile("" : : : "memory");
61        }
62#endif
63
64        uint32_t old_baud = serial_early_get_baud();
65
66        if (BFIN_DEBUG_EARLY_SERIAL) {
67                serial_early_init();
68
69                /* If the UART is off, that means we need to program
70                 * the baud rate ourselves initially.
71                 */
72                if (!old_baud) {
73                        old_baud = CONFIG_BAUDRATE;
74                        serial_early_set_baud(CONFIG_BAUDRATE);
75                }
76        }
77
78        return old_baud;
79}
80
81__attribute__((always_inline))
82static inline void serial_deinit(void)
83{
84#ifdef __ADSPBF54x__
85        if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
86                /* clear forced RTS rather than relying on auto RTS */
87                bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL);
88        }
89#endif
90}
91
92/* We need to reset the baud rate when we have early debug turned on
93 * or when we are booting over the UART.
94 * XXX: we should fix this to calc the old baud and restore it rather
95 *      than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have
96 *      to figure out how to avoid the division in the baud calc ...
97 */
98__attribute__((always_inline))
99static inline void serial_reset_baud(uint32_t baud)
100{
101        if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
102                return;
103
104#ifndef CONFIG_LDR_LOAD_BAUD
105# define CONFIG_LDR_LOAD_BAUD 115200
106#endif
107
108        if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
109                serial_early_set_baud(baud);
110        else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
111                serial_early_set_baud(CONFIG_LDR_LOAD_BAUD);
112        else
113                serial_early_set_baud(CONFIG_BAUDRATE);
114}
115
116__attribute__((always_inline))
117static inline void serial_putc(char c)
118{
119        if (!BFIN_DEBUG_EARLY_SERIAL)
120                return;
121
122        if (c == '\n')
123                *pUART_THR = '\r';
124
125        *pUART_THR = c;
126
127        while (!(*pUART_LSR & TEMT))
128                continue;
129}
130
131
132/* Max SCLK can be 133MHz ... dividing that by 4 gives
133 * us a freq of 33MHz for SPI which should generally be
134 * slow enough for the slow reads the bootrom uses.
135 */
136#ifndef CONFIG_SPI_BAUD_INITBLOCK
137# define CONFIG_SPI_BAUD_INITBLOCK 4
138#endif
139
140/* PLL_DIV defines */
141#ifndef CONFIG_PLL_DIV_VAL
142# if (CONFIG_CCLK_DIV == 1)
143#  define CONFIG_CCLK_ACT_DIV CCLK_DIV1
144# elif (CONFIG_CCLK_DIV == 2)
145#  define CONFIG_CCLK_ACT_DIV CCLK_DIV2
146# elif (CONFIG_CCLK_DIV == 4)
147#  define CONFIG_CCLK_ACT_DIV CCLK_DIV4
148# elif (CONFIG_CCLK_DIV == 8)
149#  define CONFIG_CCLK_ACT_DIV CCLK_DIV8
150# else
151#  define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
152# endif
153# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
154#endif
155
156#ifndef CONFIG_PLL_LOCKCNT_VAL
157# define CONFIG_PLL_LOCKCNT_VAL 0x0300
158#endif
159
160#ifndef CONFIG_PLL_CTL_VAL
161# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9))
162#endif
163
164#ifndef CONFIG_EBIU_RSTCTL_VAL
165# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
166#endif
167
168#ifndef CONFIG_EBIU_MBSCTL_VAL
169# define CONFIG_EBIU_MBSCTL_VAL 0
170#endif
171
172/* Make sure our voltage value is sane so we don't blow up! */
173#ifndef CONFIG_VR_CTL_VAL
174# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
175# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
176#  define CCLK_VLEV_120 400000000
177#  define CCLK_VLEV_125 533000000
178# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
179#  define CCLK_VLEV_120 401000000
180#  define CCLK_VLEV_125 401000000
181# elif defined(__ADSPBF561__)
182#  define CCLK_VLEV_120 300000000
183#  define CCLK_VLEV_125 501000000
184# endif
185# if BFIN_CCLK < CCLK_VLEV_120
186#  define CONFIG_VR_CTL_VLEV VLEV_120
187# elif BFIN_CCLK < CCLK_VLEV_125
188#  define CONFIG_VR_CTL_VLEV VLEV_125
189# else
190#  define CONFIG_VR_CTL_VLEV VLEV_130
191# endif
192# if defined(__ADSPBF52x__)     /* TBD; use default */
193#  undef CONFIG_VR_CTL_VLEV
194#  define CONFIG_VR_CTL_VLEV VLEV_110
195# elif defined(__ADSPBF54x__)   /* TBD; use default */
196#  undef CONFIG_VR_CTL_VLEV
197#  define CONFIG_VR_CTL_VLEV VLEV_120
198# endif
199
200# ifdef CONFIG_BFIN_MAC
201#  define CONFIG_VR_CTL_CLKBUF CLKBUFOE
202# else
203#  define CONFIG_VR_CTL_CLKBUF 0
204# endif
205
206# if defined(__ADSPBF52x__)
207#  define CONFIG_VR_CTL_FREQ FREQ_1000
208# else
209#  define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
210# endif
211
212# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
213#endif
214
215__attribute__((saveall))
216void initcode(ADI_BOOT_DATA *bootstruct)
217{
218        uint32_t old_baud = serial_init();
219
220#ifdef CONFIG_HW_WATCHDOG
221# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
222#  define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
223# endif
224        /* Program the watchdog with an initial timeout of ~20 seconds.
225         * Hopefully that should be long enough to load the u-boot LDR
226         * (from wherever) and then the common u-boot code can take over.
227         * In bypass mode, the start.S would have already set a much lower
228         * timeout, so don't clobber that.
229         */
230        if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
231                bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
232                bfin_write_WDOG_CTL(0);
233        }
234#endif
235
236        serial_putc('S');
237
238        /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
239         * fast read, so we need to slow down the SPI clock a lot more during
240         * boot.  Once we switch over to u-boot's SPI flash driver, we'll
241         * increase the speed appropriately.
242         */
243        if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
244#ifdef SPI0_BAUD
245                bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
246#else
247                bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
248#endif
249
250        serial_putc('B');
251
252        /* Disable all peripheral wakeups except for the PLL event. */
253#ifdef SIC_IWR0
254        bfin_write_SIC_IWR0(1);
255        bfin_write_SIC_IWR1(0);
256# ifdef SIC_IWR2
257        bfin_write_SIC_IWR2(0);
258# endif
259#elif defined(SICA_IWR0)
260        bfin_write_SICA_IWR0(1);
261        bfin_write_SICA_IWR1(0);
262#else
263        bfin_write_SIC_IWR(1);
264#endif
265
266        serial_putc('L');
267
268        bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
269
270        serial_putc('A');
271
272        /* Only reprogram when needed to avoid triggering unnecessary
273         * PLL relock sequences.
274         */
275        if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
276                serial_putc('!');
277                bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
278                asm("idle;");
279        }
280
281        serial_putc('C');
282
283        bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
284
285        serial_putc('K');
286
287        /* Only reprogram when needed to avoid triggering unnecessary
288         * PLL relock sequences.
289         */
290        if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
291                serial_putc('!');
292                bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
293                asm("idle;");
294        }
295
296        /* Since we've changed the SCLK above, we may need to update
297         * the UART divisors (UART baud rates are based on SCLK).
298         */
299        serial_reset_baud(old_baud);
300
301        serial_putc('F');
302
303        /* Program the async banks controller. */
304        bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
305        bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
306        bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
307
308#ifdef EBIU_MODE
309        /* Not all parts have these additional MMRs. */
310        bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
311        bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
312        bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
313#endif
314
315        serial_putc('I');
316
317        /* Program the external memory controller. */
318#ifdef EBIU_RSTCTL
319        bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
320        bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
321        bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
322        bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
323# ifdef CONFIG_EBIU_DDRCTL3_VAL
324        /* default is disable, so don't need to force this */
325        bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
326# endif
327#else
328        bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
329        bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
330        bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
331#endif
332
333        serial_putc('N');
334
335        /* Restore all peripheral wakeups. */
336#ifdef SIC_IWR0
337        bfin_write_SIC_IWR0(-1);
338        bfin_write_SIC_IWR1(-1);
339# ifdef SIC_IWR2
340        bfin_write_SIC_IWR2(-1);
341# endif
342#elif defined(SICA_IWR0)
343        bfin_write_SICA_IWR0(-1);
344        bfin_write_SICA_IWR1(-1);
345#else
346        bfin_write_SIC_IWR(-1);
347#endif
348
349        serial_putc('>');
350        serial_putc('\n');
351
352        serial_deinit();
353}
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