source: SVN/rincon/u-boot/cpu/ixp/npe/IxNpeMhConfig.c @ 55

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1/**
2 * @file IxNpeMhConfig.c
3 *
4 * @author Intel Corporation
5 * @date 18 Jan 2002
6 *
7 * @brief This file contains the implementation of the private API for the
8 * Configuration module.
9 *
10 *
11 * @par
12 * IXP400 SW Release version 2.0
13 *
14 * -- Copyright Notice --
15 *
16 * @par
17 * Copyright 2001-2005, Intel Corporation.
18 * All rights reserved.
19 *
20 * @par
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions
23 * are met:
24 * 1. Redistributions of source code must retain the above copyright
25 *    notice, this list of conditions and the following disclaimer.
26 * 2. Redistributions in binary form must reproduce the above copyright
27 *    notice, this list of conditions and the following disclaimer in the
28 *    documentation and/or other materials provided with the distribution.
29 * 3. Neither the name of the Intel Corporation nor the names of its contributors
30 *    may be used to endorse or promote products derived from this software
31 *    without specific prior written permission.
32 *
33 * @par
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
35 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
37 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
44 * SUCH DAMAGE.
45 *
46 * @par
47 * -- End of Copyright Notice --
48*/
49
50/*
51 * Put the system defined include files required.
52 */
53
54
55/*
56 * Put the user defined include files required.
57 */
58
59#include "IxOsal.h"
60
61#include "IxNpeMhMacros_p.h"
62
63#include "IxNpeMhConfig_p.h"
64
65/*
66 * #defines and macros used in this file.
67 */
68#define IX_NPE_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
69                                              * retries before
70                                              * timeout
71                                                                  */ 
72
73/*
74 * Typedefs whose scope is limited to this file.
75 */
76
77/**
78 * @struct IxNpeMhConfigStats
79 *
80 * @brief This structure is used to maintain statistics for the
81 * Configuration module.
82 */
83
84typedef struct
85{
86    UINT32 outFifoReads;        /**< outFifo reads */
87    UINT32 inFifoWrites;        /**< inFifo writes */
88    UINT32 maxInFifoFullRetries;   /**< max retries if inFIFO full   */
89    UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */
90} IxNpeMhConfigStats;
91
92/*
93 * Variable declarations global to this file only.  Externs are followed by
94 * static variables.
95 */
96
97IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] =
98{
99    {
100        0,
101        IX_NPEMH_NPEA_INT,
102        0,
103        0,
104        0,
105        0,
106        0,
107        NULL,
108        FALSE
109    },
110    {
111        0,
112        IX_NPEMH_NPEB_INT,
113        0,
114        0,
115        0,
116        0,
117        0,
118        NULL,
119        FALSE
120    },
121    {
122        0,
123        IX_NPEMH_NPEC_INT,
124        0,
125        0,
126        0,
127        0,
128        0,
129        NULL,
130        FALSE
131    }
132};
133
134PRIVATE IxNpeMhConfigStats ixNpeMhConfigStats[IX_NPEMH_NUM_NPES];
135
136/*
137 * Extern function prototypes.
138 */
139
140/*
141 * Static function prototypes.
142 */
143PRIVATE
144void ixNpeMhConfigIsr (void *parameter);
145
146/*
147 * Function definition: ixNpeMhConfigIsr
148 */
149
150PRIVATE
151void ixNpeMhConfigIsr (void *parameter)
152{
153    IxNpeMhNpeId npeId = (IxNpeMhNpeId)parameter;
154    UINT32 ofint;
155    volatile UINT32 *statusReg =
156        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
157
158    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
159                     "ixNpeMhConfigIsr\n");
160
161    /* get the OFINT (OutFifo interrupt) bit of the status register */
162    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofint, IX_NPEMH_NPE_STAT_OFINT);
163
164    /* if the OFINT status bit is set */
165    if (ofint)
166    {
167        /* if there is an ISR registered for this NPE */
168        if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
169        {
170            /* invoke the ISR routine */
171            ixNpeMhConfigNpeInfo[npeId].isr (npeId);
172        }
173        else
174        {
175            /* if we don't service the interrupt the NPE will continue */
176            /* to trigger the interrupt indefinitely */
177            IX_NPEMH_ERROR_REPORT ("No ISR registered to service "
178                                   "interrupt\n");
179        }
180    }
181
182    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
183                     "ixNpeMhConfigIsr\n");
184}
185
186/*
187 * Function definition: ixNpeMhConfigInitialize
188 */
189
190void ixNpeMhConfigInitialize (
191    IxNpeMhNpeInterrupts npeInterrupts)
192{
193    IxNpeMhNpeId npeId;
194    UINT32 virtualAddr[IX_NPEMH_NUM_NPES];
195
196    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
197                     "ixNpeMhConfigInitialize\n");
198
199    /* Request a mapping for the NPE-A config register address space */
200    virtualAddr[IX_NPEMH_NPEID_NPEA] =
201        (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEA_BASE,
202                                     IX_OSAL_IXP400_NPEA_MAP_SIZE);
203    IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEA]);
204
205    /* Request a mapping for the NPE-B config register address space */
206    virtualAddr[IX_NPEMH_NPEID_NPEB] =
207        (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEB_BASE,
208                                     IX_OSAL_IXP400_NPEB_MAP_SIZE);
209    IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEB]);
210   
211    /* Request a mapping for the NPE-C config register address space */
212    virtualAddr[IX_NPEMH_NPEID_NPEC] =
213        (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEC_BASE,
214                                     IX_OSAL_IXP400_NPEC_MAP_SIZE);
215    IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEC]);
216
217    /* for each NPE ... */
218    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
219    {
220        /* declare a convenience pointer */
221        IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
222       
223        /* store the virtual addresses of the NPE registers for later use */
224        npeInfo->virtualRegisterBase  = virtualAddr[npeId];
225        npeInfo->statusRegister  = virtualAddr[npeId] + IX_NPEMH_NPESTAT_OFFSET;
226        npeInfo->controlRegister = virtualAddr[npeId] + IX_NPEMH_NPECTL_OFFSET;
227        npeInfo->inFifoRegister  = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
228        npeInfo->outFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
229
230        /* for test purposes - to verify the register addresses */
231        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d status register  = "
232                         "0x%08X\n", npeId, npeInfo->statusRegister);
233        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d control register = "
234                         "0x%08X\n", npeId, npeInfo->controlRegister);
235        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d inFifo register  = "
236                         "0x%08X\n", npeId, npeInfo->inFifoRegister);
237        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d outFifo register = "
238                         "0x%08X\n", npeId, npeInfo->outFifoRegister);
239
240        /* connect our ISR to the NPE interrupt */
241        (void) ixOsalIrqBind (
242            npeInfo->interruptId, ixNpeMhConfigIsr, (void *)npeId);
243
244        /* initialise a mutex for this NPE */
245        (void) ixOsalMutexInit (&npeInfo->mutex);
246
247        /* if we should service the NPE's "outFIFO not empty" interrupt */
248        if (npeInterrupts == IX_NPEMH_NPEINTERRUPTS_YES)
249        {
250            /* enable the NPE's "outFIFO not empty" interrupt */
251            ixNpeMhConfigNpeInterruptEnable (npeId);
252        }
253        else
254        {
255            /* disable the NPE's "outFIFO not empty" interrupt */
256            ixNpeMhConfigNpeInterruptDisable (npeId);
257        }
258    }
259
260    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
261                     "ixNpeMhConfigInitialize\n");
262}
263
264/*
265 * Function definition: ixNpeMhConfigUninit
266 */
267
268void ixNpeMhConfigUninit (void)
269{
270    IxNpeMhNpeId npeId;
271
272    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
273                     "ixNpeMhConfigUninit\n");
274
275    /* for each NPE ... */
276    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
277    {
278        /* declare a convenience pointer */
279        IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
280       
281        /* disconnect ISR */
282        ixOsalIrqUnbind(npeInfo->interruptId);
283
284        /* destroy mutex associated with this NPE */
285        ixOsalMutexDestroy(&npeInfo->mutex);
286       
287        IX_OSAL_MEM_UNMAP (npeInfo->virtualRegisterBase);
288
289        npeInfo->virtualRegisterBase  = 0;
290        npeInfo->statusRegister  = 0;
291        npeInfo->controlRegister = 0;
292        npeInfo->inFifoRegister  = 0;
293        npeInfo->outFifoRegister = 0;
294    }
295
296    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
297                     "ixNpeMhConfigUninit\n");
298}
299
300/*
301 * Function definition: ixNpeMhConfigIsrRegister
302 */
303
304void ixNpeMhConfigIsrRegister (
305    IxNpeMhNpeId npeId,
306    IxNpeMhConfigIsr isr)
307{
308    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
309                     "ixNpeMhConfigIsrRegister\n");
310
311    /* check if there is already an ISR registered for this NPE */
312    if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
313    {
314        IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, "Over-writing registered NPE ISR\n");
315    }
316
317    /* save the ISR routine with the NPE info */
318    ixNpeMhConfigNpeInfo[npeId].isr = isr;
319
320    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
321                     "ixNpeMhConfigIsrRegister\n");
322}
323
324/*
325 * Function definition: ixNpeMhConfigNpeInterruptEnable
326 */
327
328BOOL ixNpeMhConfigNpeInterruptEnable (
329    IxNpeMhNpeId npeId)
330{
331    UINT32 ofe;
332    volatile UINT32 *controlReg =
333        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
334
335    /* get the OFE (OutFifoEnable) bit of the control register */
336    IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
337
338    /* if the interrupt is disabled then we must enable it */
339    if (!ofe)
340    {
341        /* set the OFE (OutFifoEnable) bit of the control register */
342        /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
343        /* time for the write to have effect */
344        IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
345                                      (IX_NPEMH_NPE_CTL_OFE |
346                                       IX_NPEMH_NPE_CTL_OFEWE),
347                                      (IX_NPEMH_NPE_CTL_OFE |
348                                       IX_NPEMH_NPE_CTL_OFEWE));
349    }
350
351    /* return the previous state of the interrupt */
352    return (ofe != 0);
353}
354
355/*
356 * Function definition: ixNpeMhConfigNpeInterruptDisable
357 */
358
359BOOL ixNpeMhConfigNpeInterruptDisable (
360    IxNpeMhNpeId npeId)
361{
362    UINT32 ofe;
363    volatile UINT32 *controlReg =
364        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
365
366    /* get the OFE (OutFifoEnable) bit of the control register */
367    IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
368
369    /* if the interrupt is enabled then we must disable it */
370    if (ofe)
371    {
372        /* unset the OFE (OutFifoEnable) bit of the control register */
373        /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
374        /* time for the write to have effect */
375        IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
376                                      (0                    |
377                                       IX_NPEMH_NPE_CTL_OFEWE),
378                                      (IX_NPEMH_NPE_CTL_OFE |
379                                       IX_NPEMH_NPE_CTL_OFEWE));
380    }
381
382    /* return the previous state of the interrupt */
383    return (ofe != 0);
384}
385
386/*
387 * Function definition: ixNpeMhConfigMessageIdGet
388 */
389
390IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
391    IxNpeMhMessage message)
392{
393    /* return the most-significant byte of the first word of the */
394    /* message */
395    return ((IxNpeMhMessageId) ((message.data[0] >> 24) & 0xFF));
396}
397
398/*
399 * Function definition: ixNpeMhConfigNpeIdIsValid
400 */
401
402BOOL ixNpeMhConfigNpeIdIsValid (
403    IxNpeMhNpeId npeId)
404{
405    /* check that the npeId parameter is within the range of valid IDs */
406    return (npeId >= 0 && npeId < IX_NPEMH_NUM_NPES);
407}
408
409/*
410 * Function definition: ixNpeMhConfigLockGet
411 */
412
413void ixNpeMhConfigLockGet (
414    IxNpeMhNpeId npeId)
415{
416    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
417                     "ixNpeMhConfigLockGet\n");
418
419    /* lock the mutex for this NPE */
420    (void) ixOsalMutexLock (&ixNpeMhConfigNpeInfo[npeId].mutex, 
421                            IX_OSAL_WAIT_FOREVER);
422
423    /* disable the NPE's "outFIFO not empty" interrupt */
424    ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
425        ixNpeMhConfigNpeInterruptDisable (npeId);
426
427    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
428                     "ixNpeMhConfigLockGet\n");
429}
430
431/*
432 * Function definition: ixNpeMhConfigLockRelease
433 */
434
435void ixNpeMhConfigLockRelease (
436    IxNpeMhNpeId npeId)
437{
438    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
439                     "ixNpeMhConfigLockRelease\n");
440
441    /* if the interrupt was previously enabled */
442    if (ixNpeMhConfigNpeInfo[npeId].oldInterruptState)
443    {
444        /* enable the NPE's "outFIFO not empty" interrupt */
445        ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
446            ixNpeMhConfigNpeInterruptEnable (npeId);
447    }
448
449    /* unlock the mutex for this NPE */
450    (void) ixOsalMutexUnlock (&ixNpeMhConfigNpeInfo[npeId].mutex);
451
452    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
453                     "ixNpeMhConfigLockRelease\n");
454}
455
456/*
457 * Function definition: ixNpeMhConfigInFifoWrite
458 */
459
460IX_STATUS ixNpeMhConfigInFifoWrite (
461    IxNpeMhNpeId npeId,
462    IxNpeMhMessage message)
463{
464    volatile UINT32 *npeInFifo =
465        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].inFifoRegister;
466    UINT32 retriesCount = 0;
467
468    /* write the first word of the message to the NPE's inFIFO */
469    IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[0]);
470
471    /* need to wait for room to write second word - see SCR #493,
472       poll for maximum number of retries, if exceed maximum
473       retries, exit from while loop */
474    while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
475        && ixNpeMhConfigInFifoIsFull (npeId))
476    {
477        retriesCount++;
478    }
479
480    /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
481    if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
482    {
483        return IX_NPEMH_CRITICAL_NPE_ERR;   
484    }   
485   
486    /* write the second word of the message to the NPE's inFIFO */
487    IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[1]);
488
489    /* record in the stats the maximum number of retries needed */
490    if (ixNpeMhConfigStats[npeId].maxInFifoFullRetries < retriesCount)
491    {
492        ixNpeMhConfigStats[npeId].maxInFifoFullRetries = retriesCount;
493    }
494
495    /* update statistical info */
496    ixNpeMhConfigStats[npeId].inFifoWrites++;
497   
498    return IX_SUCCESS;
499}
500
501/*
502 * Function definition: ixNpeMhConfigOutFifoRead
503 */
504
505IX_STATUS ixNpeMhConfigOutFifoRead (
506    IxNpeMhNpeId npeId,
507    IxNpeMhMessage *message)
508{
509    volatile UINT32 *npeOutFifo =
510        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].outFifoRegister;
511    UINT32 retriesCount = 0;
512
513    /* read the first word of the message from the NPE's outFIFO */
514    IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[0]);
515
516    /* need to wait for NPE to write second word - see SCR #493
517       poll for maximum number of retries, if exceed maximum
518       retries, exit from while loop */
519    while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
520        && ixNpeMhConfigOutFifoIsEmpty (npeId))
521    {
522        retriesCount++;
523    }
524
525    /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
526    if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
527    {
528        return IX_NPEMH_CRITICAL_NPE_ERR;   
529    } 
530   
531    /* read the second word of the message from the NPE's outFIFO */
532    IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[1]);
533
534    /* record in the stats the maximum number of retries needed */
535    if (ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries < retriesCount)
536    {
537        ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = retriesCount;
538    }
539
540    /* update statistical info */
541    ixNpeMhConfigStats[npeId].outFifoReads++;
542   
543    return IX_SUCCESS;
544}
545
546/*
547 * Function definition: ixNpeMhConfigShow
548 */
549
550void ixNpeMhConfigShow (
551    IxNpeMhNpeId npeId)
552{
553    /* show the message fifo read counter */
554    IX_NPEMH_SHOW ("Message FIFO reads",
555                   ixNpeMhConfigStats[npeId].outFifoReads);
556
557    /* show the message fifo write counter */
558    IX_NPEMH_SHOW ("Message FIFO writes",
559                   ixNpeMhConfigStats[npeId].inFifoWrites);
560
561    /* show the max retries performed when inFIFO full */
562    IX_NPEMH_SHOW ("Max inFIFO Full retries",
563                   ixNpeMhConfigStats[npeId].maxInFifoFullRetries);
564
565    /* show the max retries performed when outFIFO empty */
566    IX_NPEMH_SHOW ("Max outFIFO Empty retries",
567                   ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries);
568
569    /* show the current status of the inFifo */
570    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
571               "InFifo is %s and %s\n",
572               (ixNpeMhConfigInFifoIsEmpty (npeId) ? 
573                (int) "EMPTY" : (int) "NOT EMPTY"),
574               (ixNpeMhConfigInFifoIsFull (npeId) ? 
575                (int) "FULL" : (int) "NOT FULL"),
576               0, 0, 0, 0);
577
578    /* show the current status of the outFifo */
579    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
580               "OutFifo is %s and %s\n",
581               (ixNpeMhConfigOutFifoIsEmpty (npeId) ? 
582                (int) "EMPTY" : (int) "NOT EMPTY"),
583               (ixNpeMhConfigOutFifoIsFull (npeId) ? 
584                (int) "FULL" : (int) "NOT FULL"),
585               0, 0, 0, 0);
586}
587
588/*
589 * Function definition: ixNpeMhConfigShowReset
590 */
591
592void ixNpeMhConfigShowReset (
593    IxNpeMhNpeId npeId)
594{
595    /* reset the message fifo read counter */
596    ixNpeMhConfigStats[npeId].outFifoReads = 0;
597
598    /* reset the message fifo write counter */
599    ixNpeMhConfigStats[npeId].inFifoWrites = 0;
600
601    /* reset the max inFIFO Full retries counter */
602    ixNpeMhConfigStats[npeId].maxInFifoFullRetries = 0;
603
604    /* reset the max outFIFO empty retries counter */
605    ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = 0;
606}
607
608
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