1 | /** |
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2 | * @file QMgrQCfg.c |
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3 | * |
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4 | * @author Intel Corporation |
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5 | * @date 30-Oct-2001 |
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6 | * |
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7 | * @brief This modules provides an interface for setting up the static |
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8 | * configuration of AQM queues.This file contains the following |
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9 | * functions: |
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10 | * |
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11 | * |
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12 | * |
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13 | * @par |
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14 | * IXP400 SW Release version 2.0 |
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15 | * |
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16 | * -- Copyright Notice -- |
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17 | * |
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18 | * @par |
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19 | * Copyright 2001-2005, Intel Corporation. |
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20 | * All rights reserved. |
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21 | * |
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22 | * @par |
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23 | * Redistribution and use in source and binary forms, with or without |
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24 | * modification, are permitted provided that the following conditions |
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25 | * are met: |
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26 | * 1. Redistributions of source code must retain the above copyright |
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27 | * notice, this list of conditions and the following disclaimer. |
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28 | * 2. Redistributions in binary form must reproduce the above copyright |
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29 | * notice, this list of conditions and the following disclaimer in the |
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30 | * documentation and/or other materials provided with the distribution. |
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31 | * 3. Neither the name of the Intel Corporation nor the names of its contributors |
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32 | * may be used to endorse or promote products derived from this software |
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33 | * without specific prior written permission. |
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34 | * |
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35 | * @par |
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36 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' |
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37 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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38 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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39 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE |
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40 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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41 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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42 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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43 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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44 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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45 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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46 | * SUCH DAMAGE. |
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47 | * |
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48 | * @par |
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49 | * -- End of Copyright Notice -- |
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50 | */ |
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51 | |
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52 | /* |
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53 | * System defined include files. |
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54 | */ |
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55 | |
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56 | /* |
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57 | * User defined include files. |
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58 | */ |
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59 | #include "IxOsal.h" |
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60 | #include "IxQMgr.h" |
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61 | #include "IxQMgrAqmIf_p.h" |
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62 | #include "IxQMgrQCfg_p.h" |
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63 | #include "IxQMgrDefines_p.h" |
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64 | |
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65 | /* |
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66 | * #defines and macros used in this file. |
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67 | */ |
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68 | |
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69 | #define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16 |
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70 | |
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71 | /* Total size of SRAM */ |
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72 | #define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000 |
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73 | |
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74 | /* |
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75 | * Check that qId is a valid queue identifier. This is provided to |
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76 | * make the code easier to read. |
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77 | */ |
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78 | #define IX_QMGR_QID_IS_VALID(qId) \ |
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79 | (((qId) >= (IX_QMGR_MIN_QID)) && ((qId) <= (IX_QMGR_MAX_QID))) |
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80 | |
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81 | /* |
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82 | * Typedefs whose scope is limited to this file. |
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83 | */ |
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84 | |
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85 | /* |
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86 | * This struct describes an AQM queue. |
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87 | * N.b. bufferSizeInWords and qEntrySizeInWords are stored in the queue |
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88 | * as these are requested by Access in the data path. sizeInEntries is |
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89 | * not required by the data path so it can be calculated dynamically. |
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90 | * |
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91 | */ |
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92 | typedef struct |
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93 | { |
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94 | char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/ |
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95 | IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */ |
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96 | IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/ |
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97 | BOOL isConfigured; /* This flag is TRUE if the queue has |
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98 | * been configured |
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99 | */ |
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100 | } IxQMgrCfgQ; |
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101 | |
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102 | /* |
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103 | * Variable declarations global to this file. Externs are followed by |
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104 | * statics. |
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105 | */ |
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106 | |
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107 | extern UINT32 * ixQMgrAqmIfQueAccRegAddr[]; |
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108 | |
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109 | /* Store data required to inline read and write access |
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110 | */ |
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111 | IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[IX_QMGR_MAX_NUM_QUEUES]; |
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112 | |
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113 | static IxQMgrCfgQ cfgQueueInfo[IX_QMGR_MAX_NUM_QUEUES]; |
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114 | |
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115 | /* This pointer holds the starting address of AQM SRAM not used by |
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116 | * the AQM queues. |
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117 | */ |
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118 | static UINT32 freeSramAddress=0; |
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119 | |
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120 | /* 4 words of zeroed memory for inline access */ |
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121 | static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 }; |
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122 | |
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123 | static BOOL cfgInitialized = FALSE; |
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124 | |
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125 | static IxOsalMutex ixQMgrQCfgMutex; |
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126 | |
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127 | /* |
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128 | * Statistics |
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129 | */ |
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130 | static IxQMgrQCfgStats stats; |
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131 | |
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132 | /* |
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133 | * Function declarations |
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134 | */ |
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135 | PRIVATE BOOL |
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136 | watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level); |
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137 | |
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138 | PRIVATE BOOL |
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139 | qSizeInWordsIsOk (IxQMgrQSizeInWords qSize); |
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140 | |
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141 | PRIVATE BOOL |
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142 | qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize); |
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143 | |
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144 | /* |
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145 | * Function definitions. |
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146 | */ |
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147 | void |
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148 | ixQMgrQCfgInit (void) |
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149 | { |
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150 | int loopIndex; |
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151 | |
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152 | for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++) |
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153 | { |
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154 | /* info for code inlining */ |
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155 | ixQMgrAqmIfQueAccRegAddr[loopIndex] = zeroedPlaceHolder; |
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156 | |
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157 | /* info for code inlining */ |
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158 | ixQMgrQInlinedReadWriteInfo[loopIndex].qReadCount = 0; |
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159 | ixQMgrQInlinedReadWriteInfo[loopIndex].qWriteCount = 0; |
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160 | ixQMgrQInlinedReadWriteInfo[loopIndex].qAccRegAddr = zeroedPlaceHolder; |
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161 | ixQMgrQInlinedReadWriteInfo[loopIndex].qUOStatRegAddr = zeroedPlaceHolder; |
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162 | ixQMgrQInlinedReadWriteInfo[loopIndex].qUflowStatBitMask = 0; |
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163 | ixQMgrQInlinedReadWriteInfo[loopIndex].qOflowStatBitMask = 0; |
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164 | ixQMgrQInlinedReadWriteInfo[loopIndex].qEntrySizeInWords = 0; |
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165 | ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0; |
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166 | ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder; |
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167 | } |
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168 | |
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169 | /* Initialise the AqmIf component */ |
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170 | ixQMgrAqmIfInit (); |
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171 | |
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172 | /* Reset all queues to have queue name = NULL, entry size = 0 and |
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173 | * isConfigured = false |
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174 | */ |
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175 | for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++) |
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176 | { |
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177 | strcpy (cfgQueueInfo[loopIndex].qName, ""); |
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178 | cfgQueueInfo[loopIndex].qSizeInWords = 0; |
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179 | cfgQueueInfo[loopIndex].qEntrySizeInWords = 0; |
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180 | cfgQueueInfo[loopIndex].isConfigured = FALSE; |
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181 | |
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182 | /* Statistics */ |
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183 | stats.qStats[loopIndex].isConfigured = FALSE; |
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184 | stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName; |
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185 | } |
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186 | |
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187 | /* Statistics */ |
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188 | stats.wmSetCnt = 0; |
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189 | |
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190 | ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress); |
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191 | |
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192 | ixOsalMutexInit(&ixQMgrQCfgMutex); |
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193 | |
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194 | cfgInitialized = TRUE; |
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195 | } |
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196 | |
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197 | void |
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198 | ixQMgrQCfgUninit (void) |
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199 | { |
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200 | cfgInitialized = FALSE; |
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201 | |
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202 | /* Uninitialise the AqmIf component */ |
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203 | ixQMgrAqmIfUninit (); |
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204 | } |
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205 | |
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206 | IX_STATUS |
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207 | ixQMgrQConfig (char *qName, |
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208 | IxQMgrQId qId, |
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209 | IxQMgrQSizeInWords qSizeInWords, |
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210 | IxQMgrQEntrySizeInWords qEntrySizeInWords) |
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211 | { |
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212 | UINT32 aqmLocalBaseAddress; |
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213 | |
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214 | if (!cfgInitialized) |
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215 | { |
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216 | return IX_FAIL; |
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217 | } |
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218 | |
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219 | if (!IX_QMGR_QID_IS_VALID(qId)) |
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220 | { |
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221 | return IX_QMGR_INVALID_Q_ID; |
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222 | } |
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223 | |
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224 | else if (NULL == qName) |
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225 | { |
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226 | return IX_QMGR_PARAMETER_ERROR; |
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227 | } |
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228 | |
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229 | else if (strlen (qName) > IX_QMGR_MAX_QNAME_LEN) |
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230 | { |
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231 | return IX_QMGR_PARAMETER_ERROR; |
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232 | } |
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233 | |
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234 | else if (!qSizeInWordsIsOk (qSizeInWords)) |
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235 | { |
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236 | return IX_QMGR_INVALID_QSIZE; |
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237 | } |
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238 | |
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239 | else if (!qEntrySizeInWordsIsOk (qEntrySizeInWords)) |
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240 | { |
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241 | return IX_QMGR_INVALID_Q_ENTRY_SIZE; |
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242 | } |
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243 | |
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244 | else if (cfgQueueInfo[qId].isConfigured) |
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245 | { |
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246 | return IX_QMGR_Q_ALREADY_CONFIGURED; |
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247 | } |
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248 | |
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249 | ixOsalMutexLock(&ixQMgrQCfgMutex, IX_OSAL_WAIT_FOREVER); |
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250 | |
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251 | /* Write the config register */ |
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252 | ixQMgrAqmIfQueCfgWrite (qId, |
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253 | qSizeInWords, |
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254 | qEntrySizeInWords, |
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255 | freeSramAddress); |
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256 | |
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257 | |
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258 | strcpy (cfgQueueInfo[qId].qName, qName); |
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259 | cfgQueueInfo[qId].qSizeInWords = qSizeInWords; |
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260 | cfgQueueInfo[qId].qEntrySizeInWords = qEntrySizeInWords; |
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261 | |
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262 | /* store pre-computed information in the same cache line |
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263 | * to facilitate inlining of QRead and QWrite functions |
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264 | * in IxQMgr.h |
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265 | */ |
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266 | ixQMgrQInlinedReadWriteInfo[qId].qReadCount = 0; |
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267 | ixQMgrQInlinedReadWriteInfo[qId].qWriteCount = 0; |
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268 | ixQMgrQInlinedReadWriteInfo[qId].qEntrySizeInWords = qEntrySizeInWords; |
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269 | ixQMgrQInlinedReadWriteInfo[qId].qSizeInEntries = |
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270 | (UINT32)qSizeInWords / (UINT32)qEntrySizeInWords; |
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271 | |
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272 | /* Calculate the new freeSramAddress from the size of the queue |
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273 | * currently being configured. |
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274 | */ |
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275 | freeSramAddress += (qSizeInWords * IX_QMGR_NUM_BYTES_PER_WORD); |
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276 | |
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277 | /* Get the virtual SRAM address */ |
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278 | ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress); |
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279 | |
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280 | IX_OSAL_ASSERT((freeSramAddress - (aqmLocalBaseAddress + (IX_QMGR_QUEBUFFER_SPACE_OFFSET))) <= |
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281 | IX_QMGR_QUE_BUFFER_SPACE_SIZE); |
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282 | |
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283 | /* The queue is now configured */ |
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284 | cfgQueueInfo[qId].isConfigured = TRUE; |
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285 | |
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286 | ixOsalMutexUnlock(&ixQMgrQCfgMutex); |
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287 | |
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288 | #ifndef NDEBUG |
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289 | /* Update statistics */ |
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290 | stats.qStats[qId].isConfigured = TRUE; |
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291 | stats.qStats[qId].qName = cfgQueueInfo[qId].qName; |
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292 | #endif |
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293 | return IX_SUCCESS; |
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294 | } |
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295 | |
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296 | IxQMgrQSizeInWords |
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297 | ixQMgrQSizeInWordsGet (IxQMgrQId qId) |
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298 | { |
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299 | /* No parameter checking as this is used on the data path */ |
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300 | return (cfgQueueInfo[qId].qSizeInWords); |
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301 | } |
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302 | |
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303 | IX_STATUS |
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304 | ixQMgrQSizeInEntriesGet (IxQMgrQId qId, |
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305 | unsigned *qSizeInEntries) |
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306 | { |
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307 | if (!ixQMgrQIsConfigured(qId)) |
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308 | { |
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309 | return IX_QMGR_Q_NOT_CONFIGURED; |
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310 | } |
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311 | |
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312 | if(NULL == qSizeInEntries) |
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313 | { |
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314 | return IX_QMGR_PARAMETER_ERROR; |
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315 | } |
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316 | |
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317 | *qSizeInEntries = (UINT32)(cfgQueueInfo[qId].qSizeInWords) / |
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318 | (UINT32)cfgQueueInfo[qId].qEntrySizeInWords; |
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319 | |
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320 | return IX_SUCCESS; |
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321 | } |
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322 | |
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323 | IxQMgrQEntrySizeInWords |
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324 | ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId) |
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325 | { |
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326 | /* No parameter checking as this is used on the data path */ |
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327 | return (cfgQueueInfo[qId].qEntrySizeInWords); |
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328 | } |
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329 | |
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330 | IX_STATUS |
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331 | ixQMgrWatermarkSet (IxQMgrQId qId, |
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332 | IxQMgrWMLevel ne, |
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333 | IxQMgrWMLevel nf) |
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334 | { |
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335 | IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */ |
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336 | IxQMgrQStatus qStatusOnExit; /* to this function */ |
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337 | |
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338 | if (!ixQMgrQIsConfigured(qId)) |
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339 | { |
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340 | return IX_QMGR_Q_NOT_CONFIGURED; |
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341 | } |
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342 | |
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343 | if (!watermarkLevelIsOk (qId, ne)) |
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344 | { |
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345 | return IX_QMGR_INVALID_Q_WM; |
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346 | } |
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347 | |
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348 | if (!watermarkLevelIsOk (qId, nf)) |
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349 | { |
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350 | return IX_QMGR_INVALID_Q_WM; |
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351 | } |
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352 | |
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353 | /* Get the current queue status */ |
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354 | ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry); |
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355 | |
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356 | #ifndef NDEBUG |
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357 | /* Update statistics */ |
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358 | stats.wmSetCnt++; |
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359 | #endif |
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360 | |
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361 | ixQMgrAqmIfWatermarkSet (qId, |
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362 | ne, |
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363 | nf); |
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364 | |
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365 | /* Get the current queue status */ |
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366 | ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit); |
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367 | |
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368 | /* If the status has changed return a warning */ |
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369 | if (qStatusOnEntry != qStatusOnExit) |
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370 | { |
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371 | return IX_QMGR_WARNING; |
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372 | } |
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373 | |
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374 | return IX_SUCCESS; |
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375 | } |
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376 | |
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377 | IX_STATUS |
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378 | ixQMgrAvailableSramAddressGet (UINT32 *address, |
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379 | unsigned *sizeOfFreeRam) |
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380 | { |
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381 | UINT32 aqmLocalBaseAddress; |
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382 | |
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383 | if ((NULL == address)||(NULL == sizeOfFreeRam)) |
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384 | { |
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385 | return IX_QMGR_PARAMETER_ERROR; |
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386 | } |
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387 | if (!cfgInitialized) |
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388 | { |
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389 | return IX_FAIL; |
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390 | } |
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391 | |
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392 | *address = freeSramAddress; |
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393 | |
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394 | /* Get the virtual SRAM address */ |
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395 | ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress); |
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396 | |
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397 | /* |
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398 | * Calculate the size in bytes of free sram |
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399 | * i.e. current free SRAM virtual pointer from |
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400 | * (base + total size) |
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401 | */ |
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402 | *sizeOfFreeRam = |
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403 | (aqmLocalBaseAddress + |
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404 | IX_QMGR_AQM_SRAM_SIZE_IN_BYTES) - |
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405 | freeSramAddress; |
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406 | |
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407 | if (0 == *sizeOfFreeRam) |
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408 | { |
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409 | return IX_QMGR_NO_AVAILABLE_SRAM; |
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410 | } |
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411 | |
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412 | return IX_SUCCESS; |
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413 | } |
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414 | |
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415 | BOOL |
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416 | ixQMgrQIsConfigured (IxQMgrQId qId) |
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417 | { |
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418 | if (!IX_QMGR_QID_IS_VALID(qId)) |
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419 | { |
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420 | return FALSE; |
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421 | } |
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422 | |
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423 | return cfgQueueInfo[qId].isConfigured; |
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424 | } |
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425 | |
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426 | IxQMgrQCfgStats* |
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427 | ixQMgrQCfgStatsGet (void) |
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428 | { |
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429 | return &stats; |
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430 | } |
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431 | |
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432 | IxQMgrQCfgStats* |
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433 | ixQMgrQCfgQStatsGet (IxQMgrQId qId) |
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434 | { |
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435 | unsigned int ne; |
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436 | unsigned int nf; |
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437 | UINT32 baseAddress; |
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438 | UINT32 readPtr; |
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439 | UINT32 writePtr; |
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440 | |
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441 | stats.qStats[qId].qSizeInWords = cfgQueueInfo[qId].qSizeInWords; |
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442 | stats.qStats[qId].qEntrySizeInWords = cfgQueueInfo[qId].qEntrySizeInWords; |
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443 | |
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444 | if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries)) |
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445 | { |
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446 | if (IX_QMGR_WARNING != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries)) |
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447 | { |
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448 | IX_QMGR_LOG_WARNING1("Failed to get the number of entries in queue.... %d\n", qId); |
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449 | } |
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450 | } |
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451 | |
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452 | ixQMgrAqmIfQueCfgRead (qId, |
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453 | stats.qStats[qId].numEntries, |
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454 | &baseAddress, |
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455 | &ne, |
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456 | &nf, |
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457 | &readPtr, |
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458 | &writePtr); |
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459 | |
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460 | stats.qStats[qId].baseAddress = baseAddress; |
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461 | stats.qStats[qId].ne = ne; |
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462 | stats.qStats[qId].nf = nf; |
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463 | stats.qStats[qId].readPtr = readPtr; |
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464 | stats.qStats[qId].writePtr = writePtr; |
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465 | |
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466 | return &stats; |
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467 | } |
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468 | |
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469 | /* |
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470 | * Static function definitions |
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471 | */ |
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472 | |
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473 | PRIVATE BOOL |
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474 | watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level) |
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475 | { |
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476 | unsigned qSizeInEntries; |
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477 | |
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478 | switch (level) |
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479 | { |
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480 | case IX_QMGR_Q_WM_LEVEL0: |
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481 | case IX_QMGR_Q_WM_LEVEL1: |
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482 | case IX_QMGR_Q_WM_LEVEL2: |
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483 | case IX_QMGR_Q_WM_LEVEL4: |
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484 | case IX_QMGR_Q_WM_LEVEL8: |
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485 | case IX_QMGR_Q_WM_LEVEL16: |
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486 | case IX_QMGR_Q_WM_LEVEL32: |
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487 | case IX_QMGR_Q_WM_LEVEL64: |
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488 | break; |
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489 | default: |
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490 | return FALSE; |
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491 | } |
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492 | |
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493 | /* Check watermark is not bigger than the qSizeInEntries */ |
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494 | ixQMgrQSizeInEntriesGet(qId, &qSizeInEntries); |
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495 | |
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496 | if ((unsigned)level > qSizeInEntries) |
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497 | { |
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498 | return FALSE; |
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499 | } |
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500 | |
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501 | return TRUE; |
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502 | } |
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503 | |
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504 | PRIVATE BOOL |
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505 | qSizeInWordsIsOk (IxQMgrQSizeInWords qSize) |
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506 | { |
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507 | BOOL status; |
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508 | |
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509 | switch (qSize) |
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510 | { |
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511 | case IX_QMGR_Q_SIZE16: |
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512 | case IX_QMGR_Q_SIZE32: |
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513 | case IX_QMGR_Q_SIZE64: |
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514 | case IX_QMGR_Q_SIZE128: |
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515 | status = TRUE; |
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516 | break; |
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517 | default: |
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518 | status = FALSE; |
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519 | break; |
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520 | } |
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521 | |
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522 | return status; |
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523 | } |
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524 | |
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525 | PRIVATE BOOL |
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526 | qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize) |
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527 | { |
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528 | BOOL status; |
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529 | |
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530 | switch (entrySize) |
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531 | { |
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532 | case IX_QMGR_Q_ENTRY_SIZE1: |
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533 | case IX_QMGR_Q_ENTRY_SIZE2: |
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534 | case IX_QMGR_Q_ENTRY_SIZE4: |
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535 | status = TRUE; |
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536 | break; |
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537 | default: |
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538 | status = FALSE; |
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539 | break; |
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540 | } |
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541 | |
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542 | return status; |
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543 | } |
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