source: SVN/rincon/u-boot/cpu/ixp/npe/include/IxOsalMemAccess.h @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 18.1 KB
Line 
1/**
2 * @file IxOsalMemAccess.h
3 *
4 * @brief Header file for memory access
5 *
6 * @par
7 * @version $Revision: 1.0 $
8 *
9 * @par
10 * IXP400 SW Release version 2.0
11 *
12 * -- Copyright Notice --
13 *
14 * @par
15 * Copyright 2001-2005, Intel Corporation.
16 * All rights reserved.
17 *
18 * @par
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 * 1. Redistributions of source code must retain the above copyright
23 *    notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 *    notice, this list of conditions and the following disclaimer in the
26 *    documentation and/or other materials provided with the distribution.
27 * 3. Neither the name of the Intel Corporation nor the names of its contributors
28 *    may be used to endorse or promote products derived from this software
29 *    without specific prior written permission.
30 *
31 * @par
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42 * SUCH DAMAGE.
43 *
44 * @par
45 * -- End of Copyright Notice --
46 */
47
48#ifndef IxOsalMemAccess_H
49#define IxOsalMemAccess_H
50
51
52/* Global BE switch
53 *
54 *  Should be set only in BE mode and only if the component uses I/O memory.
55 */
56
57#if defined (__BIG_ENDIAN)
58
59#define IX_OSAL_BE_MAPPING
60
61#endif /* Global switch */
62
63
64/* By default only static memory maps in use;
65   define IX_OSAL_DYNAMIC_MEMORY_MAP per component if dynamic maps are
66   used instead in that component */
67#define IX_OSAL_STATIC_MEMORY_MAP
68
69
70/*
71 * SDRAM coherency mode
72 * Must be defined to BE, LE_DATA_COHERENT or LE_ADDRESS_COHERENT.
73 * The mode changes depending on OS
74 */
75#if defined (IX_OSAL_LINUX_BE) || defined (IX_OSAL_VXWORKS_BE)
76
77#define IX_SDRAM_BE
78
79#elif defined (IX_OSAL_VXWORKS_LE)
80
81#define IX_SDRAM_LE_DATA_COHERENT
82
83#elif defined (IX_OSAL_LINUX_LE)
84
85#define IX_SDRAM_LE_DATA_COHERENT
86
87#elif defined (IX_OSAL_WINCE_LE)
88
89#define IX_SDRAM_LE_DATA_COHERENT
90
91#elif defined (IX_OSAL_EBOOT_LE)
92
93#define IX_SDRAM_LE_ADDRESS_COHERENT
94
95#endif
96
97
98
99
100/**************************************
101 * Retrieve current component mapping *
102 **************************************/
103
104/*
105 * Only use customized mapping for LE.
106 *
107 */
108#if defined (IX_OSAL_VXWORKS_LE) || defined (IX_OSAL_LINUX_LE) || defined (IX_OSAL_WINCE_LE) || defined (IX_OSAL_EBOOT_LE)
109
110#include "IxOsalOsIxp400CustomizedMapping.h"
111
112#endif
113
114
115/*******************************************************************
116 * Turn off IX_STATIC_MEMORY map for components using dynamic maps *
117 *******************************************************************/
118#ifdef IX_OSAL_DYNAMIC_MEMORY_MAP
119
120#undef IX_OSAL_STATIC_MEMORY_MAP
121
122#endif
123
124
125/************************************************************
126 * Turn off BE access for components using LE or no mapping *
127 ************************************************************/
128
129#if ( defined (IX_OSAL_LE_AC_MAPPING) || defined (IX_OSAL_LE_DC_MAPPING) || defined (IX_OSAL_NO_MAPPING) )
130
131#undef IX_OSAL_BE_MAPPING
132
133#endif
134
135
136/*****************
137 * Safety checks *
138 *****************/
139
140/* Default to no_mapping */
141#if !defined (IX_OSAL_BE_MAPPING) && !defined (IX_OSAL_LE_AC_MAPPING) && !defined (IX_OSAL_LE_DC_MAPPING) && !defined (IX_OSAL_NO_MAPPING)
142
143#define IX_OSAL_NO_MAPPING
144
145#endif /* check at least one mapping */
146
147/* No more than one mapping can be defined for a component */
148#if   (defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_LE_AC_MAPPING))  \
149    ||(defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_LE_DC_MAPPING))  \
150    ||(defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_NO_MAPPING))     \
151    ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_NO_MAPPING))     \
152    ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING))      \
153    ||(defined (IX_OSAL_LE_AC_MAPPING) && defined (IX_OSAL_NO_MAPPING))
154
155
156#ifdef IX_OSAL_BE_MAPPING
157#warning IX_OSAL_BE_MAPPING is defined
158#endif
159
160#ifdef IX_OSAL_LE_AC_MAPPING
161#warning IX_OSAL_LE_AC_MAPPING is defined
162#endif
163
164#ifdef IX_OSAL_LE_DC_MAPPING
165#warning IX_OSAL_LE_DC_MAPPING is defined
166#endif
167
168#ifdef IX_OSAL_NO_MAPPING
169#warning IX_OSAL_NO_MAPPING is defined
170#endif
171
172#error More than one I/O mapping is defined, please check your component mapping
173
174#endif /* check at most one mapping */
175
176
177/* Now set IX_OSAL_COMPONENT_MAPPING */
178
179#ifdef IX_OSAL_BE_MAPPING
180#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_BE
181#endif
182
183#ifdef IX_OSAL_LE_AC_MAPPING
184#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_AC
185#endif
186
187#ifdef IX_OSAL_LE_DC_MAPPING
188#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_DC
189#endif
190
191#ifdef IX_OSAL_NO_MAPPING
192#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE
193#endif
194
195
196/* SDRAM coherency should be defined */
197#if !defined (IX_SDRAM_BE) && !defined (IX_SDRAM_LE_DATA_COHERENT) && !defined (IX_SDRAM_LE_ADDRESS_COHERENT)
198
199#error SDRAM coherency must be defined
200
201#endif /* SDRAM coherency must be defined */
202
203/* SDRAM coherency cannot be defined in several ways */
204#if (defined (IX_SDRAM_BE) && (defined (IX_SDRAM_LE_DATA_COHERENT) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
205    || (defined (IX_SDRAM_LE_DATA_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
206    || (defined (IX_SDRAM_LE_ADDRESS_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_DATA_COHERENT)))
207
208#error SDRAM coherency cannot be defined in more than one way
209
210#endif /* SDRAM coherency must be defined exactly once */
211
212
213/*********************
214 * Read/write macros *
215 *********************/
216
217/* WARNING - except for addition of special cookie read/write macros (see below)
218             these macros are NOT user serviceable. Please do not modify */
219
220#define IX_OSAL_READ_LONG_RAW(wAddr)          (*(wAddr))
221#define IX_OSAL_READ_SHORT_RAW(sAddr)         (*(sAddr))
222#define IX_OSAL_READ_BYTE_RAW(bAddr)          (*(bAddr))
223#define IX_OSAL_WRITE_LONG_RAW(wAddr, wData)  (*(wAddr) = (wData))
224#define IX_OSAL_WRITE_SHORT_RAW(sAddr,sData)  (*(sAddr) = (sData))
225#define IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)  (*(bAddr) = (bData))
226
227#ifdef __linux
228
229/* Linux - specific cookie reads/writes.
230  Redefine per OS if dynamic memory maps are used
231  and I/O memory is accessed via functions instead of raw pointer access. */
232
233#define IX_OSAL_READ_LONG_COOKIE(wCookie)           (readl((UINT32) (wCookie) ))
234#define IX_OSAL_READ_SHORT_COOKIE(sCookie)          (readw((UINT32) (sCookie) ))
235#define IX_OSAL_READ_BYTE_COOKIE(bCookie)           (readb((UINT32) (bCookie) ))
236#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData)   (writel(wData, (UINT32) (wCookie) ))
237#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData)  (writew(sData, (UINT32) (sCookie) ))
238#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData)   (writeb(bData, (UINT32) (bCookie) ))
239
240#endif /* linux */
241
242#ifdef __wince
243
244/* WinCE - specific cookie reads/writes. */
245
246static __inline__ UINT32
247ixOsalWinCEReadLCookie (volatile UINT32 * lCookie)
248{
249    return *lCookie;
250}
251
252static __inline__ UINT16
253ixOsalWinCEReadWCookie (volatile UINT16 * wCookie)
254{
255#if 0
256    UINT32 auxVal = *((volatile UINT32 *) wCookie);
257    if ((unsigned) wCookie & 3)
258        return (UINT16) (auxVal >> 16);
259    else
260        return (UINT16) (auxVal & 0xffff);
261#else
262    return *wCookie;
263#endif
264}
265
266static __inline__ UINT8
267ixOsalWinCEReadBCookie (volatile UINT8 * bCookie)
268{
269#if 0
270    UINT32 auxVal = *((volatile UINT32 *) bCookie);
271    return (UINT8) ((auxVal >> (3 - (((unsigned) bCookie & 3) << 3)) & 0xff));
272#else
273    return *bCookie;
274#endif
275}
276
277static __inline__ void
278ixOsalWinCEWriteLCookie (volatile UINT32 * lCookie, UINT32 lVal)
279{
280    *lCookie = lVal;
281}
282
283static __inline__ void
284ixOsalWinCEWriteWCookie (volatile UINT16 * wCookie, UINT16 wVal)
285{
286#if 0
287    volatile UINT32 *auxCookie =
288        (volatile UINT32 *) ((unsigned) wCookie & ~3);
289    if ((unsigned) wCookie & 3)
290    {
291        *auxCookie &= 0xffff;
292        *auxCookie |= (UINT32) wVal << 16;
293    }
294    else
295    {
296        *auxCookie &= ~0xffff;
297        *auxCookie |= (UINT32) wVal & 0xffff;
298    }
299#else
300    *wCookie = wVal;
301#endif
302}
303
304static __inline__ void
305ixOsalWinCEWriteBCookie (volatile UINT8 * bCookie, UINT8 bVal)
306{
307#if 0
308    volatile UINT32 *auxCookie =
309        (volatile UINT32 *) ((unsigned) bCookie & ~3);
310    *auxCookie &= 0xff << (3 - (((unsigned) bCookie & 3) << 3));
311    *auxCookie |= (UINT32) bVal << (3 - (((unsigned) bCookie & 3) << 3));
312#else
313    *bCookie = bVal;
314#endif
315}
316
317
318#define IX_OSAL_READ_LONG_COOKIE(wCookie)           (ixOsalWinCEReadLCookie(wCookie))
319#define IX_OSAL_READ_SHORT_COOKIE(sCookie)          (ixOsalWinCEReadWCookie(sCookie))
320#define IX_OSAL_READ_BYTE_COOKIE(bCookie)           (ixOsalWinCEReadBCookie(bCookie))
321#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData)   (ixOsalWinCEWriteLCookie(wCookie, wData))
322#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData)  (ixOsalWinCEWriteWCookie(sCookie, sData))
323#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData)   (ixOsalWinCEWriteBCookie(bCookie, bData))
324
325#endif /* wince */
326
327#if defined (__vxworks) || (defined (__linux) && defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
328                           (defined (__wince) && defined (IX_OSAL_STATIC_MEMORY_MAP))
329
330#define IX_OSAL_READ_LONG_IO(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
331#define IX_OSAL_READ_SHORT_IO(sAddr)           IX_OSAL_READ_SHORT_RAW(sAddr)
332#define IX_OSAL_READ_BYTE_IO(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
333#define IX_OSAL_WRITE_LONG_IO(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
334#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
335#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
336
337#elif (defined (__linux) && !defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
338      (defined (__wince) && !defined (IX_OSAL_STATIC_MEMORY_MAP))
339
340#ifndef __wince
341#include <asm/io.h>
342#endif /* ndef __wince */
343
344#define IX_OSAL_READ_LONG_IO(wAddr)            IX_OSAL_READ_LONG_COOKIE(wAddr)
345#define IX_OSAL_READ_SHORT_IO(sAddr)           IX_OSAL_READ_SHORT_COOKIE(sAddr)
346#define IX_OSAL_READ_BYTE_IO(bAddr)            IX_OSAL_READ_BYTE_COOKIE(bAddr)
347#define IX_OSAL_WRITE_LONG_IO(wAddr, wData)    IX_OSAL_WRITE_LONG_COOKIE(wAddr, wData)
348#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData)   IX_OSAL_WRITE_SHORT_COOKIE(sAddr, sData)
349#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData)    IX_OSAL_WRITE_BYTE_COOKIE(bAddr, bData)
350
351#endif
352
353/* Define BE macros */
354#define IX_OSAL_READ_LONG_BE(wAddr)          IX_OSAL_BE_BUSTOXSL(IX_OSAL_READ_LONG_IO((volatile UINT32 *) (wAddr) ))
355#define IX_OSAL_READ_SHORT_BE(sAddr)         IX_OSAL_BE_BUSTOXSS(IX_OSAL_READ_SHORT_IO((volatile UINT16 *) (sAddr) ))
356#define IX_OSAL_READ_BYTE_BE(bAddr)          IX_OSAL_BE_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
357#define IX_OSAL_WRITE_LONG_BE(wAddr, wData)  IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) (wAddr), IX_OSAL_BE_XSTOBUSL((UINT32) (wData) ))
358#define IX_OSAL_WRITE_SHORT_BE(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) (sAddr), IX_OSAL_BE_XSTOBUSS((UINT16) (sData) ))
359#define IX_OSAL_WRITE_BYTE_BE(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_BE_XSTOBUSB((UINT8) (bData) ))
360
361/* Define LE AC macros */
362#define IX_OSAL_READ_LONG_LE_AC(wAddr)          IX_OSAL_READ_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_BUSTOXSL((UINT32) (wAddr) ))
363#define IX_OSAL_READ_SHORT_LE_AC(sAddr)         IX_OSAL_READ_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_BUSTOXSS((UINT32) (sAddr) ))
364#define IX_OSAL_READ_BYTE_LE_AC(bAddr)          IX_OSAL_READ_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_BUSTOXSB((UINT32) (bAddr) ))
365#define IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)  IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_XSTOBUSL((UINT32) (wAddr) ), (UINT32) (wData))
366#define IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_XSTOBUSS((UINT32) (sAddr) ), (UINT16) (sData))
367#define IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_XSTOBUSB((UINT32) (bAddr) ), (UINT8) (bData))
368
369
370/* Inline functions are required here to avoid reading the same I/O location 2 or 4 times for the byte swap */
371static __inline__ UINT32
372ixOsalDataCoherentLongReadSwap (volatile UINT32 * wAddr)
373{
374    UINT32 wData = IX_OSAL_READ_LONG_IO (wAddr);
375    return IX_OSAL_LE_DC_BUSTOXSL (wData);
376}
377
378static __inline__ UINT16
379ixOsalDataCoherentShortReadSwap (volatile UINT16 * sAddr)
380{
381    UINT16 sData = IX_OSAL_READ_SHORT_IO (sAddr);
382    return IX_OSAL_LE_DC_BUSTOXSS (sData);
383}
384
385static __inline__ void
386ixOsalDataCoherentLongWriteSwap (volatile UINT32 * wAddr, UINT32 wData)
387{
388    wData = IX_OSAL_LE_DC_XSTOBUSL (wData);
389    IX_OSAL_WRITE_LONG_IO (wAddr, wData);
390}
391
392static __inline__ void
393ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
394{
395    sData = IX_OSAL_LE_DC_XSTOBUSS (sData);
396    IX_OSAL_WRITE_SHORT_IO (sAddr, sData);
397}
398
399/* Define LE DC macros */
400
401#define IX_OSAL_READ_LONG_LE_DC(wAddr)          ixOsalDataCoherentLongReadSwap((volatile UINT32 *) (wAddr) )
402#define IX_OSAL_READ_SHORT_LE_DC(sAddr)         ixOsalDataCoherentShortReadSwap((volatile UINT16 *) (sAddr) )
403#define IX_OSAL_READ_BYTE_LE_DC(bAddr)          IX_OSAL_LE_DC_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
404#define IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)  ixOsalDataCoherentLongWriteSwap((volatile UINT32 *) (wAddr), (UINT32) (wData))
405#define IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) ixOsalDataCoherentShortWriteSwap((volatile UINT16 *) (sAddr), (UINT16) (sData))
406#define IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_LE_DC_XSTOBUSB((UINT8) (bData)))
407
408#if defined (IX_OSAL_BE_MAPPING)
409
410#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_BE(wAddr)
411#define IX_OSAL_READ_SHORT(sAddr)               IX_OSAL_READ_SHORT_BE(sAddr)
412#define IX_OSAL_READ_BYTE(bAddr)                IX_OSAL_READ_BYTE_BE(bAddr)
413#define IX_OSAL_WRITE_LONG(wAddr, wData)        IX_OSAL_WRITE_LONG_BE(wAddr, wData)
414#define IX_OSAL_WRITE_SHORT(sAddr, sData)       IX_OSAL_WRITE_SHORT_BE(sAddr, sData)
415#define IX_OSAL_WRITE_BYTE(bAddr, bData)        IX_OSAL_WRITE_BYTE_BE(bAddr, bData)
416
417#elif defined (IX_OSAL_LE_AC_MAPPING)
418
419#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_AC(wAddr)
420#define IX_OSAL_READ_SHORT(sAddr)               IX_OSAL_READ_SHORT_LE_AC(sAddr)
421#define IX_OSAL_READ_BYTE(bAddr)                IX_OSAL_READ_BYTE_LE_AC(bAddr)
422#define IX_OSAL_WRITE_LONG(wAddr, wData)        IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
423#define IX_OSAL_WRITE_SHORT(sAddr, sData)       IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData)
424#define IX_OSAL_WRITE_BYTE(bAddr, bData)        IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)
425
426#elif defined (IX_OSAL_LE_DC_MAPPING)
427
428#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_DC(wAddr)
429#define IX_OSAL_READ_SHORT(sAddr)               IX_OSAL_READ_SHORT_LE_DC(sAddr)
430#define IX_OSAL_READ_BYTE(bAddr)                IX_OSAL_READ_BYTE_LE_DC(bAddr)
431#define IX_OSAL_WRITE_LONG(wAddr, wData)        IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
432#define IX_OSAL_WRITE_SHORT(sAddr, sData)       IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData)
433#define IX_OSAL_WRITE_BYTE(bAddr, bData)        IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)
434
435#endif   /* End of BE and LE coherency mode switch */
436
437
438/* Reads/writes to and from memory shared with NPEs - depends on the SDRAM coherency */
439
440#if defined (IX_SDRAM_BE)
441
442#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
443#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_READ_SHORT_RAW(sAddr)
444#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
445
446#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
447#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
448#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
449
450#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            (wData)
451#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           (sData)
452#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData)            (bData)
453
454#elif defined (IX_SDRAM_LE_ADDRESS_COHERENT)
455
456#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
457#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_READ_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr))
458#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr))
459
460#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
461#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr), sData)
462#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr), bData)
463
464#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            (wData)
465#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           (sData)
466#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData)            (bData)
467
468#elif defined (IX_SDRAM_LE_DATA_COHERENT)
469
470#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_SWAP_LONG(IX_OSAL_READ_LONG_RAW(wAddr))
471#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_SWAP_SHORT(IX_OSAL_READ_SHORT_RAW(sAddr))
472#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
473
474#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, IX_OSAL_SWAP_LONG(wData))
475#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, IX_OSAL_SWAP_SHORT(sData))
476#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
477
478#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            IX_OSAL_SWAP_LONG(wData)
479#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           IX_OSAL_SWAP_SHORT(sData)
480
481#endif
482
483
484#define IX_OSAL_COPY_BE_SHARED_LONG_ARRAY(wDestAddr, wSrcAddr, wCount) \
485  { \
486    UINT32 i; \
487    \
488    for ( i = 0 ; i < wCount ; i++ ) \
489    { \
490      * (((UINT32 *) wDestAddr) + i) = IX_OSAL_READ_BE_SHARED_LONG(((UINT32 *) wSrcAddr) + i); \
491    }; \
492  };
493
494#endif /* IxOsalMemAccess_H */
Note: See TracBrowser for help on using the repository browser.