source: SVN/rincon/u-boot/cpu/ixp/npe/include/IxQueueAssignments.h @ 55

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1/**
2 * @file IxQueueAssignments.h
3 *
4 * @author Intel Corporation
5 * @date 29-Oct-2004
6 *
7 * @brief Central definition for queue assignments
8 *
9 * Design Notes:
10 * This file contains queue assignments used by Ethernet (EthAcc),
11 * HSS (HssAcc), ATM (atmdAcc) and DMA (dmaAcc) access libraries.
12 *
13 * Note: Ethernet QoS traffic class definitions are managed separately
14 * by EthDB in IxEthDBQoS.h.
15 *
16 * @par
17 * IXP400 SW Release version 2.0
18 *
19 * -- Copyright Notice --
20 *
21 * @par
22 * Copyright 2001-2005, Intel Corporation.
23 * All rights reserved.
24 *
25 * @par
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
28 * are met:
29 * 1. Redistributions of source code must retain the above copyright
30 *    notice, this list of conditions and the following disclaimer.
31 * 2. Redistributions in binary form must reproduce the above copyright
32 *    notice, this list of conditions and the following disclaimer in the
33 *    documentation and/or other materials provided with the distribution.
34 * 3. Neither the name of the Intel Corporation nor the names of its contributors
35 *    may be used to endorse or promote products derived from this software
36 *    without specific prior written permission.
37 *
38 * @par
39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
42 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
45 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
46 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
47 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
48 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
49 * SUCH DAMAGE.
50 *
51 * @par
52 * -- End of Copyright Notice --
53 */
54
55#ifndef IxQueueAssignments_H
56#define IxQueueAssignments_H
57
58#include "IxQMgr.h"
59
60/***************************************************************************
61 *  Queue assignments for ATM
62 ***************************************************************************/
63
64/**
65 * @brief Global compiler switch to select between 3 possible NPE Modes
66 * Define this macro to enable MPHY mode
67 *
68 * Default(No Switch) = MultiPHY Utopia2
69 * IX_UTOPIAMODE = 1 for single Phy Utopia1
70 * IX_MPHYSINGLEPORT = 1 for single Phy Utopia2
71 */
72#define IX_NPE_MPHYMULTIPORT 1
73#if IX_UTOPIAMODE == 1
74#undef  IX_NPE_MPHYMULTIPORT
75#endif
76#if IX_MPHYSINGLEPORT == 1
77#undef  IX_NPE_MPHYMULTIPORT
78#endif
79
80/**
81 * @def IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
82 *
83 * @brief The NPE reserves the High Watermark for its operation. But it must be set by the Xscale
84 */
85#define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK  2
86
87/**
88 * @def IX_NPE_A_QMQ_ATM_TX_DONE
89 *
90 * @brief Queue ID for ATM Transmit Done queue
91 */
92#define IX_NPE_A_QMQ_ATM_TX_DONE       IX_QMGR_QUEUE_1
93
94/**
95 * @def IX_NPE_A_QMQ_ATM_TX0
96 *
97 * @brief Queue ID for ATM transmit Queue in a single phy configuration
98 */
99#define IX_NPE_A_QMQ_ATM_TX0           IX_QMGR_QUEUE_2
100
101
102/**
103 * @def IX_NPE_A_QMQ_ATM_TXID_MIN
104 *
105 * @brief Queue Manager Queue ID for ATM transmit Queue with minimum number of queue
106 *
107 */
108
109/**
110 * @def IX_NPE_A_QMQ_ATM_TXID_MAX
111 *
112 * @brief Queue Manager Queue ID for ATM transmit Queue with maximum number of queue
113 *
114 */
115
116/**
117 * @def IX_NPE_A_QMQ_ATM_RX_HI
118 *
119 * @brief Queue Manager Queue ID for ATM Receive high Queue
120 *
121 */
122
123/**
124 * @def IX_NPE_A_QMQ_ATM_RX_LO
125 *
126 * @brief Queue Manager Queue ID for ATM Receive low Queue
127 */
128
129#ifdef IX_NPE_MPHYMULTIPORT
130/**
131 * @def IX_NPE_A_QMQ_ATM_TX1
132 *
133 * @brief Queue ID for ATM transmit Queue Multiphy from 1 to 11
134 */
135#define IX_NPE_A_QMQ_ATM_TX1           IX_NPE_A_QMQ_ATM_TX0+1
136#define IX_NPE_A_QMQ_ATM_TX2           IX_NPE_A_QMQ_ATM_TX1+1
137#define IX_NPE_A_QMQ_ATM_TX3           IX_NPE_A_QMQ_ATM_TX2+1
138#define IX_NPE_A_QMQ_ATM_TX4           IX_NPE_A_QMQ_ATM_TX3+1
139#define IX_NPE_A_QMQ_ATM_TX5           IX_NPE_A_QMQ_ATM_TX4+1
140#define IX_NPE_A_QMQ_ATM_TX6           IX_NPE_A_QMQ_ATM_TX5+1
141#define IX_NPE_A_QMQ_ATM_TX7           IX_NPE_A_QMQ_ATM_TX6+1
142#define IX_NPE_A_QMQ_ATM_TX8           IX_NPE_A_QMQ_ATM_TX7+1
143#define IX_NPE_A_QMQ_ATM_TX9           IX_NPE_A_QMQ_ATM_TX8+1
144#define IX_NPE_A_QMQ_ATM_TX10          IX_NPE_A_QMQ_ATM_TX9+1
145#define IX_NPE_A_QMQ_ATM_TX11          IX_NPE_A_QMQ_ATM_TX10+1
146#define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
147#define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX11
148#define IX_NPE_A_QMQ_ATM_RX_HI         IX_QMGR_QUEUE_21
149#define IX_NPE_A_QMQ_ATM_RX_LO         IX_QMGR_QUEUE_22
150#else
151#define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
152#define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX0
153#define IX_NPE_A_QMQ_ATM_RX_HI         IX_QMGR_QUEUE_10
154#define IX_NPE_A_QMQ_ATM_RX_LO         IX_QMGR_QUEUE_11
155#endif /* MPHY */
156
157/**
158 * @def IX_NPE_A_QMQ_ATM_FREE_VC0
159 *
160 * @brief Hardware QMgr Queue ID for ATM Free VC Queue.
161 *
162 * There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to
163 * IX_NPE_A_QMQ_ATM_FREE_VC30
164 */
165#define IX_NPE_A_QMQ_ATM_FREE_VC0      IX_QMGR_QUEUE_32
166#define IX_NPE_A_QMQ_ATM_FREE_VC1      IX_NPE_A_QMQ_ATM_FREE_VC0+1
167#define IX_NPE_A_QMQ_ATM_FREE_VC2      IX_NPE_A_QMQ_ATM_FREE_VC1+1
168#define IX_NPE_A_QMQ_ATM_FREE_VC3      IX_NPE_A_QMQ_ATM_FREE_VC2+1
169#define IX_NPE_A_QMQ_ATM_FREE_VC4      IX_NPE_A_QMQ_ATM_FREE_VC3+1
170#define IX_NPE_A_QMQ_ATM_FREE_VC5      IX_NPE_A_QMQ_ATM_FREE_VC4+1
171#define IX_NPE_A_QMQ_ATM_FREE_VC6      IX_NPE_A_QMQ_ATM_FREE_VC5+1
172#define IX_NPE_A_QMQ_ATM_FREE_VC7      IX_NPE_A_QMQ_ATM_FREE_VC6+1
173#define IX_NPE_A_QMQ_ATM_FREE_VC8      IX_NPE_A_QMQ_ATM_FREE_VC7+1
174#define IX_NPE_A_QMQ_ATM_FREE_VC9      IX_NPE_A_QMQ_ATM_FREE_VC8+1
175#define IX_NPE_A_QMQ_ATM_FREE_VC10     IX_NPE_A_QMQ_ATM_FREE_VC9+1
176#define IX_NPE_A_QMQ_ATM_FREE_VC11     IX_NPE_A_QMQ_ATM_FREE_VC10+1
177#define IX_NPE_A_QMQ_ATM_FREE_VC12     IX_NPE_A_QMQ_ATM_FREE_VC11+1
178#define IX_NPE_A_QMQ_ATM_FREE_VC13     IX_NPE_A_QMQ_ATM_FREE_VC12+1
179#define IX_NPE_A_QMQ_ATM_FREE_VC14     IX_NPE_A_QMQ_ATM_FREE_VC13+1
180#define IX_NPE_A_QMQ_ATM_FREE_VC15     IX_NPE_A_QMQ_ATM_FREE_VC14+1
181#define IX_NPE_A_QMQ_ATM_FREE_VC16     IX_NPE_A_QMQ_ATM_FREE_VC15+1
182#define IX_NPE_A_QMQ_ATM_FREE_VC17     IX_NPE_A_QMQ_ATM_FREE_VC16+1
183#define IX_NPE_A_QMQ_ATM_FREE_VC18     IX_NPE_A_QMQ_ATM_FREE_VC17+1
184#define IX_NPE_A_QMQ_ATM_FREE_VC19     IX_NPE_A_QMQ_ATM_FREE_VC18+1
185#define IX_NPE_A_QMQ_ATM_FREE_VC20     IX_NPE_A_QMQ_ATM_FREE_VC19+1
186#define IX_NPE_A_QMQ_ATM_FREE_VC21     IX_NPE_A_QMQ_ATM_FREE_VC20+1
187#define IX_NPE_A_QMQ_ATM_FREE_VC22     IX_NPE_A_QMQ_ATM_FREE_VC21+1
188#define IX_NPE_A_QMQ_ATM_FREE_VC23     IX_NPE_A_QMQ_ATM_FREE_VC22+1
189#define IX_NPE_A_QMQ_ATM_FREE_VC24     IX_NPE_A_QMQ_ATM_FREE_VC23+1
190#define IX_NPE_A_QMQ_ATM_FREE_VC25     IX_NPE_A_QMQ_ATM_FREE_VC24+1
191#define IX_NPE_A_QMQ_ATM_FREE_VC26     IX_NPE_A_QMQ_ATM_FREE_VC25+1
192#define IX_NPE_A_QMQ_ATM_FREE_VC27     IX_NPE_A_QMQ_ATM_FREE_VC26+1
193#define IX_NPE_A_QMQ_ATM_FREE_VC28     IX_NPE_A_QMQ_ATM_FREE_VC27+1
194#define IX_NPE_A_QMQ_ATM_FREE_VC29     IX_NPE_A_QMQ_ATM_FREE_VC28+1
195#define IX_NPE_A_QMQ_ATM_FREE_VC30     IX_NPE_A_QMQ_ATM_FREE_VC29+1
196#define IX_NPE_A_QMQ_ATM_FREE_VC31     IX_NPE_A_QMQ_ATM_FREE_VC30+1
197
198/**
199 * @def IX_NPE_A_QMQ_ATM_RXFREE_MIN
200 *
201 * @brief The minimum queue ID for FreeVC queue
202 */
203#define IX_NPE_A_QMQ_ATM_RXFREE_MIN  IX_NPE_A_QMQ_ATM_FREE_VC0
204
205/**
206 * @def IX_NPE_A_QMQ_ATM_RXFREE_MAX
207 *
208 * @brief The maximum queue ID for FreeVC queue
209 */
210#define IX_NPE_A_QMQ_ATM_RXFREE_MAX  IX_NPE_A_QMQ_ATM_FREE_VC31
211
212/**
213 * @def IX_NPE_A_QMQ_OAM_FREE_VC
214 * @brief OAM Rx Free queue ID
215 */
216#ifdef IX_NPE_MPHYMULTIPORT
217#define IX_NPE_A_QMQ_OAM_FREE_VC       IX_QMGR_QUEUE_14
218#else
219#define IX_NPE_A_QMQ_OAM_FREE_VC       IX_QMGR_QUEUE_3
220#endif /* MPHY */
221
222/****************************************************************************
223 * Queue assignments for HSS
224 ****************************************************************************/
225
226/****  HSS Port 0 ****/
227
228/**
229 * @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
230 *
231 * @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
232 */
233#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG   IX_QMGR_QUEUE_12
234
235/**
236 * @def IX_NPE_A_QMQ_HSS0_PKT_RX
237 *
238 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive
239 */
240#define IX_NPE_A_QMQ_HSS0_PKT_RX        IX_QMGR_QUEUE_13
241
242/**
243 * @def IX_NPE_A_QMQ_HSS0_PKT_TX0
244 *
245 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0
246 */
247#define IX_NPE_A_QMQ_HSS0_PKT_TX0       IX_QMGR_QUEUE_14
248
249/**
250 * @def IX_NPE_A_QMQ_HSS0_PKT_TX1
251 *
252 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1
253 */
254#define IX_NPE_A_QMQ_HSS0_PKT_TX1       IX_QMGR_QUEUE_15
255
256/**
257 * @def IX_NPE_A_QMQ_HSS0_PKT_TX2
258 *
259 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2
260 */
261#define IX_NPE_A_QMQ_HSS0_PKT_TX2       IX_QMGR_QUEUE_16
262
263/**
264 * @def IX_NPE_A_QMQ_HSS0_PKT_TX3
265 *
266 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3
267 */
268#define IX_NPE_A_QMQ_HSS0_PKT_TX3       IX_QMGR_QUEUE_17
269
270/**
271 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
272 *
273 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0
274 */
275#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0  IX_QMGR_QUEUE_18
276
277/**
278 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
279 *
280 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1
281 */
282#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1  IX_QMGR_QUEUE_19
283
284/**
285 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
286 *
287 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2
288 */
289#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2  IX_QMGR_QUEUE_20
290
291/**
292 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
293 *
294 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3
295 */
296#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3  IX_QMGR_QUEUE_21
297
298/**
299 * @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
300 *
301 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue
302 */
303#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE   IX_QMGR_QUEUE_22
304
305/****  HSS Port 1 ****/
306
307/**
308 * @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
309 *
310 * @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger
311 */
312#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG   IX_QMGR_QUEUE_10
313
314/**
315 * @def IX_NPE_A_QMQ_HSS1_PKT_RX
316 *
317 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive
318 */
319#define IX_NPE_A_QMQ_HSS1_PKT_RX        IX_QMGR_QUEUE_0
320
321/**
322 * @def IX_NPE_A_QMQ_HSS1_PKT_TX0
323 *
324 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0
325 */
326#define IX_NPE_A_QMQ_HSS1_PKT_TX0       IX_QMGR_QUEUE_5
327
328/**
329 * @def IX_NPE_A_QMQ_HSS1_PKT_TX1
330 *
331 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1
332 */
333#define IX_NPE_A_QMQ_HSS1_PKT_TX1       IX_QMGR_QUEUE_6
334
335/**
336 * @def IX_NPE_A_QMQ_HSS1_PKT_TX2
337 *
338 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2
339 */
340#define IX_NPE_A_QMQ_HSS1_PKT_TX2       IX_QMGR_QUEUE_7
341
342/**
343 * @def IX_NPE_A_QMQ_HSS1_PKT_TX3
344 *
345 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3
346 */
347#define IX_NPE_A_QMQ_HSS1_PKT_TX3       IX_QMGR_QUEUE_8
348
349/**
350 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
351 *
352 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0
353 */
354#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0  IX_QMGR_QUEUE_1
355
356/**
357 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
358 *
359 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1
360 */
361#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1  IX_QMGR_QUEUE_2
362
363/**
364 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
365 *
366 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2
367 */
368#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2  IX_QMGR_QUEUE_3
369
370/**
371 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
372 *
373 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3
374 */
375#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3  IX_QMGR_QUEUE_4
376
377/**
378 * @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
379 *
380 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue
381 */
382#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE   IX_QMGR_QUEUE_9
383
384/*****************************************************************************************
385 * Queue assignments for DMA
386 *****************************************************************************************/
387
388#define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19   /**< Queue Id for NPE A DMA Request */
389#define IX_DMA_NPE_A_DONE_QID    IX_QMGR_QUEUE_20   /**< Queue Id for NPE A DMA Done    */
390#define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24   /**< Queue Id for NPE B DMA Request */
391#define IX_DMA_NPE_B_DONE_QID    IX_QMGR_QUEUE_26   /**< Queue Id for NPE B DMA Done    */
392#define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25   /**< Queue Id for NPE C DMA Request */
393#define IX_DMA_NPE_C_DONE_QID    IX_QMGR_QUEUE_27   /**< Queue Id for NPE C DMA Done    */
394
395
396/*****************************************************************************************
397 * Queue assignments for Ethernet
398 *
399 * Note: Rx queue definitions, which include QoS traffic class definitions
400 * are managed by EthDB and declared in IxEthDBQoS.h
401 *****************************************************************************************/
402
403/**
404*
405* @def IX_ETH_ACC_RX_FRAME_ETH_Q
406*
407* @brief  Eth0/Eth1 NPE Frame Recieve Q.
408*
409* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
410*
411*/
412#define IX_ETH_ACC_RX_FRAME_ETH_Q       (IX_QMGR_QUEUE_4)
413
414/**
415*
416* @def IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q
417*
418* @brief Supply Rx Buffers Ethernet Q for NPEB - Eth 0 - Port 1
419*
420*/
421#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q    (IX_QMGR_QUEUE_27)
422
423/**
424*
425* @def IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q
426*
427* @brief Supply Rx Buffers Ethernet Q for NPEC - Eth 1 - Port 2
428*
429*/
430#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q    (IX_QMGR_QUEUE_28)
431
432/**
433*
434* @def IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q
435*
436* @brief Supply Rx Buffers Ethernet Q for NPEA - Eth 2 - Port 3
437*
438*/
439#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q    (IX_QMGR_QUEUE_26)
440
441
442/**
443*
444* @def IX_ETH_ACC_TX_FRAME_ENET0_Q
445*
446* @brief Submit frame Q for NPEB Eth 0 - Port 1
447*
448*/
449#define IX_ETH_ACC_TX_FRAME_ENET0_Q    (IX_QMGR_QUEUE_24)
450
451
452/**
453*
454* @def IX_ETH_ACC_TX_FRAME_ENET1_Q
455*
456* @brief Submit frame Q for NPEC Eth 1 - Port 2
457*
458*/
459#define IX_ETH_ACC_TX_FRAME_ENET1_Q    (IX_QMGR_QUEUE_25)
460
461/**
462*
463* @def IX_ETH_ACC_TX_FRAME_ENET2_Q
464*
465* @brief Submit frame Q for NPEA Eth 2 - Port 3
466*
467*/
468#define IX_ETH_ACC_TX_FRAME_ENET2_Q    (IX_QMGR_QUEUE_23)
469
470/**
471*
472* @def IX_ETH_ACC_TX_FRAME_DONE_ETH_Q
473*
474* @brief Transmit complete Q for NPE Eth 0/1, Port 1&2
475*
476*/
477#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q    (IX_QMGR_QUEUE_31)
478
479/*****************************************************************************************
480 * Queue assignments for Crypto
481 *****************************************************************************************/
482
483/** Crypto Service Request Queue */
484#define IX_CRYPTO_ACC_CRYPTO_REQ_Q  (IX_QMGR_QUEUE_29)
485
486/** Crypto Service Done Queue */
487#define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)
488
489/** Crypto Req Q CB tag */
490#define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG   (0)
491
492/** Crypto Done Q CB tag */
493#define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG  (1)
494
495/** WEP Service Request Queue */
496#define IX_CRYPTO_ACC_WEP_REQ_Q  (IX_QMGR_QUEUE_21)
497
498/** WEP Service Done Queue */
499#define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)
500
501/** WEP Req Q CB tag */
502#define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG      (2)
503
504/** WEP Done Q CB tag */
505#define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG     (3)
506
507/** Number of queues allocate to crypto hardware accelerator services */
508#define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q       (2)
509
510/** Number of queues allocate to WEP NPE services */
511#define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q      (2)
512                                                     
513/** Number of queues allocate to CryptoAcc component */
514#define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)   
515
516#endif /* IxQueueAssignments_H */
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