source: SVN/rincon/u-boot/cpu/lh7a40x/speed.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 2.3 KB
Line 
1/*
2 * (C) Copyright 2001-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2002
6 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <lh7a40x.h>
29
30
31/* ------------------------------------------------------------------------- */
32/* NOTE: This describes the proper use of this file.
33 *
34 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
35 *
36 * get_FCLK(), get_HCLK(), get_PCLK() return the clock of
37 * the specified bus in HZ.
38 */
39/* ------------------------------------------------------------------------- */
40
41ulong get_PLLCLK (void)
42{
43        return CONFIG_SYS_CLK_FREQ;
44}
45
46/* return FCLK frequency */
47ulong get_FCLK (void)
48{
49        lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
50        ulong maindiv1, maindiv2, prediv, ps;
51
52        /*
53         * from userguide 6.1.1.2
54         *
55         * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
56         *                   ((PREDIV+2) * (2^PS))
57         */
58        maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
59        maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
60        prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
61        ps = (csc->clkset & CLKSET_PS) >> 16;
62
63        return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
64                ((prediv + 2) * (1 << ps)));
65}
66
67
68/* return HCLK frequency */
69ulong get_HCLK (void)
70{
71        lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
72
73        return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1));
74}
75
76/* return PCLK frequency */
77ulong get_PCLK (void)
78{
79        lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
80
81        return (get_HCLK () /
82                (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1)));
83}
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