source: SVN/rincon/u-boot/cpu/mcf52x2/speed.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 2.6 KB
Line 
1/*
2 * (C) Copyright 2003
3 * Josef Baumgartner <josef.baumgartner@telex.de>
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * Hayden Fraser (Hayden.Fraser@freescale.com)
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/processor.h>
29#include <asm/immap.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
33/*
34 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
35 */
36int get_clocks (void)
37{
38#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
39        volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
40        unsigned long pllcr;
41
42#ifndef CFG_PLL_BYPASS
43
44#ifdef CONFIG_M5249
45        /* Setup the PLL to run at the specified speed */
46#ifdef CFG_FAST_CLK
47        pllcr = 0x925a3100;     /* ~140MHz clock (PLL bypass = 0) */
48#else
49        pllcr = 0x135a4140;     /* ~72MHz clock (PLL bypass = 0) */
50#endif
51#endif                          /* CONFIG_M5249 */
52
53#ifdef CONFIG_M5253
54        pllcr = CFG_PLLCR;
55#endif                          /* CONFIG_M5253 */
56
57        cpll = cpll & 0xfffffffe;       /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
58        mbar2_writeLong(MCFSIM_PLLCR, cpll);    /* Set the PLL to bypass mode (PSTCLK = crystal) */
59        mbar2_writeLong(MCFSIM_PLLCR, pllcr);   /* set the clock speed */
60        pllcr ^= 0x00000001;    /* Set pll bypass to 1 */
61        mbar2_writeLong(MCFSIM_PLLCR, pllcr);   /* Start locking (pll bypass = 1) */
62        udelay(0x20);           /* Wait for a lock ... */
63#endif                          /* #ifndef CFG_PLL_BYPASS */
64
65#endif                          /* CONFIG_M5249 || CONFIG_M5253 */
66
67#if defined(CONFIG_M5275)
68        volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
69
70        /* Setup PLL */
71        pll->syncr = 0x01080000;
72        while (!(pll->synsr & FMPLL_SYNSR_LOCK))
73                ;
74        pll->syncr = 0x01000000;
75        while (!(pll->synsr & FMPLL_SYNSR_LOCK))
76                ;
77#endif
78
79        gd->cpu_clk = CFG_CLK;
80#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
81        gd->bus_clk = gd->cpu_clk / 2;
82#else
83        gd->bus_clk = gd->cpu_clk;
84#endif
85
86#ifdef CONFIG_FSL_I2C
87        gd->i2c1_clk = gd->bus_clk;
88#ifdef CFG_I2C2_OFFSET
89        gd->i2c2_clk = gd->bus_clk;
90#endif
91#endif
92
93        return (0);
94}
Note: See TracBrowser for help on using the repository browser.