Changes between Version 16 and Version 17 of PCI


Ignore:
Timestamp:
09/01/2023 03:54:48 PM (8 months ago)
Author:
Tim Harvey
Comment:

updated venice PCI capability table

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  • PCI

    v16 v17  
    88Gateworks PCI support:
    99||= Product Family =||= Capabilities =||
    10 || Venice  GW71xx/GW72xx/GW73xx/GW74xx (IMX8MM) || PCIe Gen2 ^^^3^^^ ||
     10|| Venice  GW74xx (IMX8MP) || PCIe Gen2 ^^^4^^^ ||
     11|| Venice  GW71xx/GW72xx/GW73xx (IMX8MM) || PCIe Gen2 ^^^3^^^ ||
     12|| ||
    1113|| Newport GW64xx   || PCIe Gen3 ||
    1214|| Newport GW61xx/GW62xx/GW63xx || PCIe Gen2 ^^^2^^^ ||
     15|| ||
    1316|| Ventana          || PCIe Gen1 ^^^1^^^ ||
    1417 1. Ventana boards with external clock generators can theoretically support Gen2 however some software modification would be necessary for the PCIe clock configuration.
    1518 2. Newport can support PCIe Gen3 via a Gateworks special which modifies a strapping resistor to move the coprocessor clock (SCLK) from 350MHz to 550Mhz (at the cost of ~500mW of power draw).
    1619 3. Venice i.MX 8M has a limitation when the inbound write data transfer size exceeds 400 Bytes, the number of inbound MWr TLP transactions the controller can support is up to the combination of 12 hearders and 400 bytes of data (see [https://comm.eefocus.com/media/download/index/id-1021154 AN13164 iMX8MP PCIe Bandwidth Analysis]. Higher performance can be obtained by having the i.MX 8M Plus issue outbound MRd transactions instead of using inbound MWr.
     20 4. While the IMX8MP supports PCIe Gen3 the GW74xx has a Gen2 switch on it so only supports Gen2
    1721
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