Changes between Version 8 and Version 9 of PCI


Ignore:
Timestamp:
06/18/2020 07:23:14 PM (2 years ago)
Author:
Tim Harvey
Comment:

added see also links, table of gateworks board pci capabilities, and throughput section

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  • PCI

    v8 v9  
    11[[PageOutline]]
     2
     3See also:
     4 * [wiki:newport/PCIe]
     5 * [wiki:ventana/PCIe]
     6
     7Gateworks PCI support:
     8||= Product Family =||= Capabilities =||
     9|| Venice           || PCIe Gen2 ||
     10|| Newport          || PCIe Gen2 ^^^2^^^ ||
     11|| Ventana          || PCIe Gen1 ^^^1^^^ ||
     12 1. Ventana boards with external clock generators can theoretically support Gen2 however some software modification would be necessary for the PCIe clock configuration.
     13 2. Newport can support PCIe Gen3 via a Gateworks special which modifies a strapping resistor to move the coprocessor clock (SCLK) from 350MHz to 550Mhz (at the cost of ~500mW of power draw).
    214
    315= PCI
     
    4961Modern generation Gateworks products such as the Laguna GW2391, Ventana, and Newport product families support Mini PCIe cards.
    5062
     63[=#throughput]
     64= PCI Throughput
     65The PCI specification has evolved to support various generations capable of increasing bus speeds:
     66 * PCI Gen3 (8.0GT/sec or 6.4Gbps)
     67 * PCI Gen2 (5.0GT/sec or 4Gbps)
     68 * PCI Gen1 (2.5GT/sec or 2Gbps)
     69
     70These are backwards compatible such that a PCI Gen3 link will only be established if the device and host controller support it and otherwise it will step down to Gen2 then Gen1 as needed.
     71
     72The bus speed represents a theoretical maximum throughput and does not account for host processing speed or bus contention from multiple masters.
    5173
    5274[=#linux-pci-debug]