[[PageOutline]] = PCI Peripheral Component Interconnect (PCI) is part of the PCI Local Bus standard. The PCI bus supports the functions found on a processor bus and Devices connected to the PCI bus appear to a bus master to be connected directly to its own bus and are assigned addresses in the processor's address space. Bus mastering refers to the concept that PCI devices can directly access a processors memory bus independent of the processor similar to a Direct Memory Access (DMA) controller. PCI History: * PCI 1.9 1992 Original issue * PCI 2.0 1993 Incorporated connector and add-in card specification * PCI 2.1 1995 Incorporated clarifications and added 66 MHz * PCI 2.2 1998 Added Mini PCI, Incorporated ECNs and improved readability * PCI 2.3 2002 Incorporated ECNs, errata, and deleted 5 volt only keyed add-in cards * PCI 3.0 2004 Removed support for 5.0 volt keyed system board connector * PCI Express 2004 Conventional PCI had 4 shared level-triggered interrupts and uses a paralle bus architecture where the PCI host and all devices share a common set of address, data and control lines. References: * https://en.wikipedia.org/wiki/Conventional_PCI = Mini PCI Mini PCI was added to PCI version 2.2 and differs from Conventional PCI in the following ways: * 32bit 33Mhz * 3.3V only; 5V limited to 100mA * three form factors: - Type I card uses a 100pin stacking connector - Type II card uses a 100pin stacking connector and accomodates a larger size - Type III card uses a 124pin edge connector Older generation Gateworks products such as some Laguna product families support the Mini PCI Type III cards. = PCI Express (PCIe) While the original PCI bus, now referred to as 'Conventional PCI' was a parallel bus with shared address/data in 2004 The PCI Express (PCIe) specification was released which defined a serialized version of PCI which is commonplace today. PCI Express is based on a point-to-point topology with separate serial links connecting every device to the host, also known as the root complex (RC). Links may contain from one to 32 lanes (1x, 2x, 4x, 12x, 16x, 32x) with each lane being its own differential pair. PCI Express interrupts are embedded within the serial data. References: * https://en.wikipedia.org/wiki/PCI_Express = PCI Express Mini Card (also known as 'Mini PCIe', 'mPCIe' or 'PEM') The PCI Express Mini Card specification is based on PCI Express with the following differences: * uses a 52-pin edge connector with 2 rows of pins * incorporates both 1x (1 lane) PCI Express, USB 2.0, and SIM connectivity on the connector Modern generation Gateworks products such as the Laguna GW2391, Ventana, and Newport product families support Mini PCIe cards. [=#linux-pci-debug] = Linux PCI Debugging PCI configuration registers can be used to debug various PCI bus issues. The easiest way to access these registers is via the Linux {{{lspci}}} command with the 'very verbose' flag (-vv) which will decode and display the various PCI config space registers. Note that access to some parts of the PCI configuration space is restricted to root permissions on many operating systems - if this is the case you will see certain data flagged as 'access denied'. The various registers define bits that are either set (indicated with a '+') or unset (indicated with a '-'). These bits typically have attributes of 'RW1C' meaning you can read and write them and need to write a '1' to clear them. Because these are status bits, if you wanted to 'count' the occurrences of them you would need to write some software that detected the bits getting set, incremented counters, and cleared them over time. The 'Device Status Register' (!DevSta) shows at a high level if there have been correctable errors detected (!CorrErr), non-fatal errors detected (!UncorrErr), fata errors detected (!FataErr), unsupported requests detected (!UnsuppReq), if the device requires auxillary power (!AuxPwr), and if there are transactions pending (non posted requests that have not been completed). If you want to delve deeper into types of errors see [#aer PCI Advanced Error Reporting] below. References: - [https://www.kernel.org/doc/ols/2007/ols2007v2-pages-297-304.pdf Enable PCI Express Advanced Error Reporting in the Kernel] - [http://composter.com.ua/documents/PCI_Express_Base_Specification_Revision_3.0.pdf PCI Express Base Specification Revision 3.0] - [https://intrepid.warped.com/~scotte/OldBlogEntries/web/index-5.html PCI Debugging 101] [=#aer] == PCI Advanced Error Reporting (AER) Most modern PCI devices support 'Advanced Error Reporting' (AER). For these devices a {{{lspci -vv}}} as root will show additional registers similar to the ones described above: * UESta - Uncorrectable Error Status * UEMsk - Uncorrectable Error Mask * UESvrt - Uncorrectable Error Severity * CESta - Correctable Error Status * CEMsk - Correctable Error Mask * AERCap - Advanced Error Reporting Capabilities For specifics on what the meaning of the bits in these registers are see the PCI Express Base Specification Revision 3.0] == Examples Here are some examples: * Show all Atheros/QCA radios on the PCI bus (vendor 168c): {{{#!bash $ lspci -n | grep 168c 0001:20:00.0 0280: 168c:0046 }}} * Very Verbose listing of a specific device: {{{#!bash $ sudo lspci -s 1:20:00 -vv 0001:20:00.0 Network controller: Qualcomm Atheros Device 0046 Subsystem: Qualcomm Atheros Device cafe Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR-