Changes between Version 14 and Version 15 of SPI

Timestamp:

12/19/2019 12:37:18 AM (4 years ago)

Author:

Cale Collins

Comment:

explain half duplex SPI in more detail

SPI

@@ -29 +29 @@
 || ||
 || Laguna   || GW2388    || J9        || ||
- 1. Note that the Cavium ThunderX SPI controller in the CN80XX on the Newport Product family only supports half-duplex SPI transfers. Drivers that use full-duplex transactions can be modified to support half-duplex (see [https://github.com/Gateworks/linux-newport/commit/cb270339619ccf2b50dfd3604a03626f85830453 'can:mcp251x: convert driver to half-duplex SPI'] as en example.
+ 1. Note that the Cavium ThunderX SPI controller in the CN80XX on the Newport Product family only supports half-duplex SPI transfers.  In hardware the connections are full duplex MISO and MOSI lines are not shared, in software reads and writes need to be sent in separate calls, rather than simultaneously (full duplex).  Drivers that use full-duplex transactions can be modified to support half-duplex (see [https://github.com/Gateworks/linux-newport/commit/cb270339619ccf2b50dfd3604a03626f85830453 'can:mcp251x: convert driver to half-duplex SPI'] as en example.
  2. While only a single Chip Select (CS) is brought out to an external connector and of the DIO pins routed to ARM GPIO's can be used as additional chip-selects. For Ventana this is done via device-tree pinctrl and for Newport this must be done via a PINSEL GPIO (contact support@gateworks.com)
  3. Note that the Cavium ThunderX SPI controller in the CN80XX only supports SPI mode 1 (which clock polarity (CPOL/CKP) is low, clock phase (CPHA) is high, and Clock edge (CKE/NCPHA) is low.