Changes between Initial Version and Version 1 of expansion/gw16113


Ignore:
Timestamp:
10/22/2017 05:28:45 AM (2 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • expansion/gw16113

    v1 v1  
     1[[PageOutline]]
     2
     3= GW16113 miniPCIe Expansion Module =
     4The GW16113 is a miniPCIe expansion module that offers a flexible variety of I/O and function by using a Cypress PSoC 5LP.
     5
     6'''The GW16113 is currently under design but we are sharing preliminary specs'''
     7
     8== Features ==
     9Preliminary Specifications:
     10 * miniPCIe form-factor
     11 * miniPCIe socket providing PCIe signalling and USB signalling pass-through
     12 * 3x 10pin Port connectors:
     13  * 1x 3.3V power pin
     14  * 1x ground
     15  * 8x I/O (24 total) 3.3V TTL with various termination configurations
     16 * USB FS interface to host processor
     17 * on-board USB hub (to provide USB pass-through to miniPCIe socket)
     18 * 2x surface mount green user-controllable LED's
     19
     20Gateworks will offer the GW16113 pre-programmed with a specific firmware configuration. Preliminary Specifications:
     21 * 8x [#GeneralPurposeIOGPIO GPIO] (8 pins) with configurable modes
     22 * 2x [#UniversalAsynchronousReceiverTransmitterUART UART] (2 pins: TX, RX) (No RS232)
     23 * 1x [#I2CInterface I2C master/multi-master/slave] (2 pins: SCL, SDA)
     24 * 1x [#SerialPeripheralInterfaceSPI SPI master] (3 pins: MISO, MOSI, SCLK)
     25 * 1x [#ControllerAreaNetworkCAN CAN controller] (3 pins: TX, RX, TX_EN)
     26 * 1x [#DeltaSigmaAnalogtoDigitalConverterADC_DelSig ADC] (1 pin: 20-bit Delta Sigma)
     27 * 1x [#SequencingSuccessiveApproximationADC ADC] (1 pin: 12-bit Successive Approximation (SAR))
     28 * 2x [#DigitaltoAnalogConverterDAC DAC] (2 pins: Configurable waveform generation, voltage or current source/sink)
     29 * 2x [#OnBoardLEDs LED] (no external pins)
     30
     31
     32== I/O pins ==
     33Thw 24 I/O terminals available on the GW16113 are 3.3V TTL level
     34
     35Pin I/O details:
     36 * Voltage
     37||= Parameter =||= Description                =||= Min =||= Max =||= Comment       =||
     38|| V,,GPIO,,   || Range of Input Voltage       || -0.5V || 3.8V  || V,,SSD,,-0.5 to V,,DDD,,+0.5 ||
     39|| V,,MIN,,    || Maximum Input voltage        ||       || 3.8V  || V,,DDD,,+0.5  ||
     40|| V,,IH,,     || Input voltage high threshold || 2.31V || -     || 0.7 x V,,DDIO,, ||
     41|| V,,IL,,     || Input voltage low threshold  || -     || 0.99V || 0.3 x V,,DDIO,, ||
     42|| V,,OH,,     || Output voltage high          || 2.9V  || -     || V,,DDIO,,-0.4 ||
     43|| V,,OL,,     || Output voltage low           || -     || 0.8V  || I,,OL,, = 25mA  ||
     44  * See [http://www.cypress.com/documentation/datasheets/psoc-5lp-cy8c58lp-family-datasheet-programmable-system-chip-psoc?source=search&cat=technical_documents CY8C58LP datasheet] section 11.4 for more details
     45 * Current capabilities
     46||= Parameter =||= Description       =||= Source =||= Sink  =||= Notes =||
     47|| I,,GPIO,,   || J2/P3,J1/P0 current || 4 mA     || 8 mA    ||         ||
     48|| I,,SIO,,    || J1/P12 current      || 4 mA     || 25 mA   || '''1''' ||
     49   * See [http://www.cypress.com/documentation/datasheets/psoc-5lp-cy8c58lp-family-datasheet-programmable-system-chip-psoc?source=search&cat=technical_documents CY8C58LP datasheet] Figure 11-8 and 11-9 for GPIO (J2/P3 and J1/P0) output curves
     50   * See [http://www.cypress.com/documentation/datasheets/psoc-5lp-cy8c58lp-family-datasheet-programmable-system-chip-psoc?source=search&cat=technical_documents CY8C58LP datasheet] Figure 11-10 and 11-11 for SIO (J1/P12) output curves
     51   1. '''The GW16113 has 332 ohm series termination resistors between the PSoC pins and the external connectors limiting the current to 10mA - contact sales@gateworks.com for information on creating a Gateworks special with modified termination'''
     52
     53
     54== Customizable Firmware ==
     55Multiple pre-built firmware configurations may be available for download [http://svn.gateworks.com/gwsoc/ here].
     56
     57Users can also choose to customize the firmware on their own to suit their needs. The Gateworks PSoC Creator source is available [https://github.com/Gateworks/gwsoc here]. The [http://www.cypress.com/psoccreator/ Cypress PSoC Creator] is the free Windows development tool provided by Cypress used to design and compile firmware for PSoC devices.
     58
     59The GW16113 uses the [http://www.cypress.com/products/cy8c58lpxxx CY8C58LP] (part number: CY8C5888LTI-LP097) from the  [http://www.cypress.com/products/psoc-5lp PSoC5LP family] which has the following:
     60 * 32bit ARM Cortex-M3 CPU with 32 interrupts
     61 * 24-channel DMA controller
     62 * 24-bit 64-tap fixed-point digital filter processor (DFB)
     63 * 256KB program flash
     64 * 64KB RAM
     65 * 2KB EEPROM
     66 * Digital peripherals:
     67  * 4x 16bit timer, counter and PWM blocks
     68  * 1x I2C controller (up to 1mbps speed)
     69  * 1x USB 2.0 Full-Speed (FS) (12mbps) '''(not available for use - this is how we communicate to the host processor)'''
     70  * 1x CAN 2.0b (16rx / 8tx bufers)
     71  * 20 to 24 universal digital blocks (UDB) programmable to create any number of functions:
     72   * 8-, 16-, 24-, and 32-bit timers, counters and PWMs
     73   * I2C, UART, SPI, I2S, LIN 2.0 interfaces
     74   * CRC blocks
     75   * Pseudo random sequence (PRS) generators
     76   * Quadrature decoders
     77   * Gate-level logic functions
     78 * Programmable clocking
     79 * Analog peripherals:
     80  * Configurable 8- to 20-bit delta-sigma ADC
     81  * 2x 12-bit SAR ADCs
     82  * 4x 8bit DACs
     83  * 4x comparators
     84  * 4x opamps
     85  * 4x programmable analog blocks to create:
     86   * Programmable gain amplifier (PGA)
     87   * Transimpedance amplifier (TIA)
     88   * Mixer
     89   * Sample and hold circuit
     90 * Cypress !CapSense support
     91 * 1.024V +/- 0.1% internal voltage reference
     92 * LCD direct drive from any GPIO
     93
     94References:
     95 * [http://www.gateworks.com/product/item/ventana-gw16113-expansion-adapter GW16113 Product Page]
     96
     97
     98[=#firmwareimages]
     99=== Firmware Images ===
     100The current firmware images available from Gateworks [http://svn.gateworks.com/gwsoc/ here] are:
     101 * GW16113_HID_GPIO - Vendor-ID/Product-ID: 0x2beb:0x1110 - '''beta - current factory default'''
     102 * GW16113_Composite Vendor-ID/Product-ID: 0x2beb:0x1113 - '''coming soon'''
     103
     104The firmware resides in the 256KB PSoC FLASH therefore is non-volatile and contains both the  bootloader as well as the main application. See [#firmwareupdate below] regarding firmware updates.
     105
     106
     107[=#firmwareupdate]
     108=== Firmware Updates ===
     109The PSoC has 256KB of programmable non-volatile FLASH that are used to contain the 'firmware application'. The pre-built firmware images provided by Gateworks contain a PSoC5 Bootloader application that allows for USB updates of the main application (aka bootloadable) firmware.
     110
     111GW16113 bootloader details:
     112 * Bootloader is programmed at the factory via JTAG and is not able to be updated via USB (technically an application firmware can be created that allows updating the bootloader however Gateworks does not currently support this)
     113 * USB Vendor-ID and Product-ID of bootloader: 0x2beb:0x1100
     114 * Bootloader application is run when GW16113 comes out of reset (when PCI_RESET# is released) and will do one of the following depending on EEPROM configuration:
     115  1. remain in the bootloader awaiting a command (to jump to existing app, or program new app)
     116  2. remain in the bootloader awaiting a command if the state of the I/O ports latched coming out of reset matches a predefined value, otherwise jump to the application immediately
     117  3. jump directly to application
     118 * main application can be instructed to jump to the bootloader and wait for a command (to allow firmware updating)
     119
     120Options 1 and 2 above are designed to provide a fool-proof way of recovering from a failed firmware update, or faulty firmware that does not allow a method to jump back to the bootloader.
     121
     122The factory default configuration is to stay in the bootloader a logic value of 0x55 (pin1,3,5,7 logic high, pin2,4,6,8 logic low) is latched on P12 (J1) when the GW16113 comes out of reset (option 2 above).
     123
     124The bootloader configuration is stored in the PSoC EEPROM and can be altered via the [#gwsoc gwsoc] application (or directly by the main application if using custom firmware) if the default configuration does not suit your needs.
     125
     126The [#gwsoc gwsoc] application running on the host processor has the ability to instruct the application to jump to the bootloader and await a command for updating the main application firmware. The '-p' command-line option is used to update the firmware providing a '.cyacd' file.
     127
     128Examples:
     129 * program GW16113_HID-GPIO firmware:
     130{{{
     131wget http://svn.gateworks.com/gwsoc/gw16113/GW16113_HID-GPIO.cyacd
     132gwsoc -p GW16113_HID-GPIO.cyacd
     133}}}
     134
     135If for some reason the use case demands the 15KB FLASH space (of 256KB available) used by the bootloader or the ability to update the firmware via USB is not desired, the firmware can be customized by the user to eliminate the bootloader. The resulting firmware would need to be programmed via JTAG. Contact sales@gateworks.com if this is a requirement.
     136
     137References:
     138 * [file:///home/tharvey/Downloads/Bootloadable_Bootloader_001-92648.pdf Bootloader and Bootloadable Component Datasheet]
     139
     140=== General Purpose IO (GPIO) ===
     141The I/O pins allows a variety of Drive Modes:
     142 * strong drive
     143 * open drain, drives high
     144 * open drain, drives low
     145 * resistive pull-up (5.6kOhm typ)
     146 * resistive pull-down (5.6kOhm typ)
     147 * resistive pull up/down (5.6kOhm typ)
     148 * high impedance digital
     149 * high impedance analog
     150
     151Several GPIO's will likely be able to be configured with different capabilities:
     152 * [http://www.cypress.com/documentation/component-datasheets/pulse-width-modulator-pwm?source=search&keywords=pwm&cat=software_tools PWM]
     153
     154
     155The USB API will allow the following:
     156 * get/set I/O direction (input/output)
     157 * get/set digital logic level
     158 * set digital logic level
     159 * configure power-up pin drive mode
     160
     161Reference:
     162 * [http://www.cypress.com/file/137401/download Pins component datasheet]
     163 * [http://www.cypress.com/file/137416/download PWM component datasheet]
     164
     165
     166
     167=== Universal Asynchronous Receiver Transmitter (UART) ===
     168The [http://www.cypress.com/documentation/component-datasheets/software-transmit-uart-swtxuart?source=search&keywords=uart&cat=software_tools Universal Asynchronous Receiver Transmitter (UART) Component] Features
     169 * 9-bit address mode with hardware address detection
     170 * Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps
     171 * RX and TX buffers = 4 to 65535
     172 * Detection of Framing, Parity, and Overrun errors
     173 * Full Duplex, Half Duplex, TX only, and RX only optimized hardware
     174 * Two out of three voting per bit
     175 * Break signal generation and detection
     176 * 8x or 16x oversampling
     177
     178The PSoC 5LP does not have fixed hardware UART blocks but instead uses resources from the UDB array.
     179
     180The USB API will allow the following:
     181 * read/write data
     182 * configure data communications
     183
     184Note that there are no transceivers on the GW16113 therefore all signalling is 3.3V TTL level and if RS232 signalling is necessary an RS232 transceiver would be needed off-board.
     185
     186Reference:
     187 * [http://www.cypress.com/file/177171/download UART component datasheet]
     188
     189
     190
     191=== I2C Interface ===
     192The [http://www.cypress.com/documentation/component-datasheets/i2c-mastermulti-masterslave?source=search&keywords=i2c&cat=software_tools I2C component] supports I2C slave, master, and multi-master configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices.
     193
     194The I2C component supports standard clock speeds up to 1mbps and is compatible with I2C standard mode, fast mode, and fast mode plus devices as defines in the NXP I2C-bus specification.
     195
     196Features:
     197 * supports slave / master / multi-master and multi-master-slave operation
     198 * 2 pin standard I^2^C bus
     199 * supports standard data rates of 100 / 400 / 1000kbps
     200
     201The PSoC 5LP has 1 fixed hardware I2C block and can provide additional I2C components via UDB blocks.
     202
     203The USB API will allow the following:
     204 * read/write data
     205 * configure data communications
     206
     207
     208Reference:
     209 * [http://www.cypress.com/file/175671/download I2C component datasheet]
     210
     211
     212=== Serial Peripheral Interface (SPI) ===
     213The [http://www.cypress.com/documentation/component-datasheets/serial-peripheral-interface-spi-master?source=search&keywords=spi&cat=software_tools Serial Peripheral Interface (SPI) Master component] features:
     214 * 3 to 16bit data width
     215 * four SPI operation modes
     216 * bitrate up to 18mbps
     217
     218The PSoC 5LP does not have a fixed hardware SPI master interface but instead uses resources from the UDB array. There is both a SPI Master component and SPI Slave component available but the default configuration for the GW16113 will support the master.
     219
     220The USB API will allow the following:
     221 * read/write data
     222 * configure data communications
     223
     224Reference:
     225 * [http://www.cypress.com/file/135226/download SPI Master component datasheet]
     226
     227
     228=== Controller Area Network (CAN) ===
     229The [http://www.cypress.com/documentation/component-datasheets/controller-area-network-can?source=search&keywords=can&cat=software_tools Controller Area Network component] has the following features:
     230 * CAN2.0A and CAN2.0B protocol implementation, ISO 11898-1 compliant
     231 * Programmable bit rate up to 1 Mbps at 8 MHz (BUS_CLK)
     232 * Two-wire or three-wire interface to external transceiver (Tx, Rx, and Enable)
     233 * Extended hardware message filter that covers Data Byte 1 and Data Byte 2 fields
     234 * Programmable transmit priority: Round Robin and Fixed
     235
     236Note that the GW16113 does not have a CAN transceiver. The external pinout will be 3.3V TTL and a CAN transceiver and termination would need to be available off-board.
     237
     238The USB API will allow the following:
     239 * read/write data
     240 * configure data communications
     241
     242Reference:
     243 * [http://www.cypress.com/file/135116/download Controller Area Network component datasheet]
     244
     245
     246=== Delta Sigma Analog to Digital Converter (ADC_DelSig) ===
     247The [http://www.cypress.com/documentation/component-datasheets/delta-sigma-analog-digital-converter-adcdelsig?source=search&keywords=adc&cat=software_tools Delta Sigma Analog to Digital Converter (ADC_DelSig)] has the following features:
     248 * Selectable resolutions, 8 to 20 bits
     249 * Eleven input ranges for each resolution
     250 * Sample rate 8 sps to 384 ksps
     251 * Operational modes:
     252  * Single sample
     253  * Multi-sample
     254  * Continuous mode
     255  * Multi-sample (Turbo)
     256 * High input impedance input buffer
     257  * Selectable input buffer gain (1, 2, 4, 8) or input buffer bypass
     258 * Multiple internal or external reference options
     259 * Automatic power configuration
     260 * Up to four run-time ADC configurations
     261
     262The USB API will allow the following:
     263 * start/stop conversion
     264 * read ADC value
     265 * select input buffer gain
     266
     267Reference:
     268 * [http://www.cypress.com/file/135096/download Delta Sigma Analog to Digital Converter component datasheet]
     269
     270
     271=== Sequencing Successive Approximation ADC ===
     272The [http://www.cypress.com/documentation/component-datasheets/adc-successive-approximation-register-adcsar?source=search&keywords=adc&cat=software_tools Sequencing Successive Approximation (SAR) ADC component] provides a 12-bit successive approximation with conversions up to 1M samples per second and a signal to noise ratio better than 70dB.
     273
     274Features:
     275 * selectable resolution (8, 10, 12 bit)
     276 * selectable sample rate (up to 1 Msps)
     277
     278The USB API will allow the following:
     279 * start/stop conversion
     280 * read ADC value
     281 * configure resolution and samplerate
     282
     283Reference:
     284 * [http://www.cypress.com/file/135101/download Sequencing Successive Approximation (SAR) ADC component datasheet]
     285
     286
     287=== Digital to Analog Converter (DAC) ===
     288The [http://www.cypress.com/documentation/component-datasheets/8-bit-waveform-generator-wavedac8?source=search&keywords=dac&cat=software_tools 8-Bit Waveform Generator] features include:
     289 * Supports standard and arbitrary waveform generation or static voltage driven or current source/sink value
     290 * Arbitrary waveform may be drawn manually or imported from file
     291 * Output may be voltage or current, sink or source
     292 * Voltage output can be buffered or direct from DAC
     293 * Hardware selection between two waveforms
     294 * Waveforms may be up to 4000 points
     295 * Predefined sine, triangle, square, and sawtooth waveforms
     296
     297The USB API will allow the following:
     298 * start/stop output
     299 * configure waveform (with 4 to 4000 sample points)
     300 * configure drive mode and speed
     301 * select current or voltage mode
     302
     303Reference:
     304 * [http://www.cypress.com/file/135271/download 8-Bit Waveform Generator component datasheet]
     305
     306
     307=== On Board LEDs ===
     308There are two on-board LED's that can be turned on or off.
     309
     310The USB API will allow the following:
     311 * enable/disable LED
     312
     313
     314== Software Support ==
     315
     316'''The following is preliminary information and is subject to change'''
     317
     318There are two pieces of software dealing with the GW16113:
     319 1. The GW16113 firmware that is flashed onto the PSoc chip
     320 2. The userspace program that controls the GPIOs, etc
     321
     322=== Linux Userspace Utilities ===
     323
     324[=#gwsoc]
     325==== gwsoc ====
     326Gateworks will provide a {{{gwsoc}}} command-line utility which will make use of the popular open-source and cross-platform HIDAPI and libusb libraries for:
     327 * updating firmware (the firmware dictates the feature matrix for the I/O pins)
     328 * accessing the various features (ie configuring GPIO's etc).
     329
     330The {{{gwsoc}}} application will come pre-installed on the various Gateworks Board Support Package (BSP) firmware images. Source-code is also provided (see [#gsoc-building building gwsoc])
     331
     332The {{{gwsoc}}} application currently is what is used to get/set GPIO configuration using 32bit registers mapped as follows on the GW16113:
     333||= bit =||= PSoC Port / Pin =||= GW16113 =||
     334|| 0     || P12.0 (SIO)     || J1.1                ||
     335|| 1     || P12.1 (SIO)     || J1.2                ||
     336|| 2     || P12.2 (SIO)     || J1.3                ||
     337|| 3     || P12.3 (SIO)     || J1.4                ||
     338|| 4     || P12.4 (SIO)     || J1.5                ||
     339|| 5     || P12.5 (SIO)     || J1.6                ||
     340|| 6     || P12.6 (SIO)     || J1.7                ||
     341|| 7     || P12.7 (SIO)     || J1.8                ||
     342|| 8     || P3.0  (GPIO)    || J2.1                ||
     343|| 9     || P3.1  (GPIO)    || J2.2                ||
     344|| 10    || P3.2  (GPIO)    || J2.3                ||
     345|| 11    || P3.3  (GPIO)    || J2.4                ||
     346|| 12    || P3.4  (GPIO)    || J2.5                ||
     347|| 13    || P3.5  (GPIO)    || J2.6                ||
     348|| 14    || P3.6  (GPIO)    || J2.7                ||
     349|| 15    || P3.7  (GPIO)    || J2.8                ||
     350|| 16    || P0.0  (GPIO)    || J3.1                ||
     351|| 17    || P0.1  (GPIO)    || J3.2                ||
     352|| 18    || P0.2  (GPIO)    || J3.3                ||
     353|| 19    || P0.3  (GPIO)    || J3.4                ||
     354|| 20    || P0.4  (GPIO)    || J3.5                ||
     355|| 21    || P0.5  (GPIO)    || J3.6                ||
     356|| 22    || P0.6  (GPIO)    || J3.7                ||
     357|| 23    || P0.7  (GPIO)    || J3.8                ||
     358|| 24    || unused          ||                     ||
     359|| 25    || unused          ||                     ||
     360|| 26    || unused          ||                     ||
     361|| 27    || unused          ||                     ||
     362|| 28    || unused          ||                     ||
     363|| 29    || unused          ||                     ||
     364|| 30    || P2.0  (GPIO)    || D7 LED (read-only)  ||
     365|| 31    || P2.1  (GPIO)    || D8 LED (read-only)  ||
     366
     367Example usage:
     368 * show usage:
     369{{{
     370# gwsoc
     371GWSoC Utility v1.00
     372usage: gwsoc  [-p filename] [gpio[=val]] [gpiodir[=val]] [config<n>[=<val>]]
     373}}}
     374 * program GW16113_HID-GPIO firmware:
     375{{{
     376# gwsoc -p GW16113_HID-GPIO.cyacd
     377}}}
     378 * get gpio direction register:
     379{{{
     380# gwsoc gpiodir
     381GWSoC Utility v1.00
     382GWSoC_HID: 0x2beb:0x1110 Gateworks Corporation GW16113_HID_GPIO 660070
     383gpiodir=0x00ffffff
     384}}}
     385   * the value of 0x00ffffff (bit0-23 set) indicate that all I/O's are configured for input
     386 * set gpio direction register (set bit for input, clear for output):
     387{{{
     388# gwsoc gpiodir=0x00ff00ff
     389GWSoC Utility v1.00
     390GWSoC_HID: 0x2beb:0x1110 Gateworks Corporation GW16113_HID_GPIO 660070
     391gpiodir=0x00ff00ff
     392}}}
     393  * the value of 0x00ff00ff (bit0-7,16-23 set) configures P12 (J1) and P0 (J3) as inputs and P3 (J2) as outputs
     394 * set gpio data register (set bit to drive high, clear to drive low)
     395{{{
     396# gwsoc gpio=0x00005500
     397GWSoC Utility v1.00
     398GWSoC_HID: 0x2beb:0x1110 Gateworks Corporation GW16113_HID_GPIO 660070
     399gpio=0x00005500
     400}}}
     401  * the value of 0x00005500 indicates to drive P3.0,2,4,6 cooresponding to J2.1,3,5,7 logic high
     402 * get gpio data register:
     403{{{
     404# gwsoc gpio
     405GWSoC Utility v1.00
     406GWSoC_HID: 0x2beb:0x1110 Gateworks Corporation GW16113_HID_GPIO 660070
     407gpio=0x00005500
     408}}}
     409  * the value of 0x00005555 indicates that P12.0,2,4,6 cooresponding to J1.1,3,5,7 are reading high (these are inputs per the gpiodir setting above) and P3.0,2,4,6 cooresponding to J2.1,3,5,7 are outputing logic high
     410
     411
     412[=#gwsoc-building]
     413===== Building gwsoc from source =====
     414To build the gwsoc application on an Ubuntu Linux host:
     415{{{
     416git clone http://github.com/Gateworks/gwsoc
     417cd gwsoc/gwsoc
     418sudo aptitude install libudev-dev libusb-1.0-0-dev libhidapi-dev # install dependencies
     419make
     420}}}
     421
     422You may also want to install a udev rule to allow group ownership of hid devices for the plugdev group:
     423{{{
     424# cat /etc/udev/rules.d/99-hid.rules
     425KERNEL=="hidraw*", SUBSYSTEM=="hidraw", MODE="0664", GROUP="plugdev"
     426}}}
     427
     428
     429[=#drivers]
     430=== Linux Device Drivers ===
     431Linux native kernel drivers will be provided in the Gateworks Board Support Packages '''(coming soon)'''.
     432
     433
     434== PSoc 5LP and Firmware ==
     435The GW16113 is based upon the Cypress PSoC 5LP device which is a programmable device which can be best thought of as cross between a microcontroller combined with a PLD and programmable analog. This means that the board can operate in many different modes depending on how it is programmed.
     436
     437References:
     438 * [http://www.cypress.com/products/cy8c58lpxxx PSoC 5LP Product page]
     439 * [http://www.cypress.com/file/45906/download PSoC5LP CY8C58LP Family Datasheet]
     440 * [http://www.cypress.com/search/all?f%5B0%5D=meta_type%3Asoftware_tools&f%5B1%5D=software_tools_meta_type%3A532 PSoC5LP Component list]
     441 * [http://www.cypress.com/file/123561/download PSoC5LP Architecture Technical Reference Manual (TRM)]
     442
     443
     444=== PSoC Resources and Capabilities ===
     445Cypress provides pre-configured functional blocks referred to as 'Components' that can be supported by the PSoC. Conceptually these are '''virtual peripherals''' that each have their own datasheet, schematic library representation, and support code implementing an API.
     446
     447The [http://www.cypress.com/psoccreator/ Cypress PSoC Creator] is the free Windows development tool provided by Cypress used to design and compile firmware for PSoC devices. To create firmware that can be programmed on a PSoC you use this tool to drag-and-drop and configure schematic representations of components and edit ANSI-C code to configure and control the components.
     448
     449A list of components compatible with the PSoC 5LP is available from Cypress [http://www.cypress.com/search/all?f%5B0%5D=meta_type%3Asoftware_tools&f%5B1%5D=software_tools_meta_type%3A532 PSoC5LP here] and all of these are available within PSoC Creator.
     450
     451Each PSoC 5LP has a fixed set of internal resources available such as:
     452 * RAM
     453 * FLASH storage
     454 * Univeral Design Blocks (UDB)
     455 * Digital clock dividers
     456 * Pins
     457 * DMA channels
     458 * Comparators
     459 * Programmable Analog Blocks
     460 * Interrupts
     461 * various Fixed blocks (ie USB, CAN, I2C, SPI, UART, controllers)
     462
     463Each component has its own individual datasheet that contains details such as:
     464 * Features
     465 * Software API
     466 * Hardware configuration info
     467 * Resource usage
     468
     469To determine what can fit into a PSoC you can compare the PSoC datasheet list of resources with the individual component datasheets. Preferably PSoC Creator can generate a resource summary by:
     470 * Workspace Explorer -> Results Tab -> Select the usage report file titled <project-name>.rpt
     471 * Build -> Generate Project Datasheet (refer to section 2)
     472
     473Cypress also has a nifty online tool that knows quite a bit about what each component needs and what is available. It is used for selecting a PSoC chip but can also be useful to prove that your basic needs can be met. You can find their epsg tool [http://www.cypress.com/epsg/ here]. Note that this tool does not take into account that we only have 24 I/O pins available to connectors.
     474
     475References:
     476 * [http://www.cypress.com/search/all?f%5B0%5D=meta_type%3Asoftware_tools&f%5B1%5D=software_tools_meta_type%3A532 PSoC5LP Component Datasheets]
     477
     478=== Programming PSoc Firmware ===
     479 1. Compile the firmware using the PSoc creator detailed above
     480 2. Copy the file to the Gateworks SBC board that has the GW16113 installed
     481 3. Verify the gwsoc software is accessible via the command line on the Gateworks SBC
     482 4. Verify the USB code is still present in the new firmware image as this code is used to access and update the PSoc and without it, the board could be bricked.
     483 5. Program the firmware to the GW16113 with the program flag in the gwsoc application
     484{{{
     485gwsoc -p {filename}
     486}}}
     487
     488== Cable and Connector Information ==
     489Cables are sold seperately.
     490
     491[wiki:alternateconnectors#GW16113ExpansionCardCableInformation Please see information here]