| 60 | | |
| 61 | | == Customizable Firmware == |
| 62 | | Pre-built firmware configurations may be available for download [http://dev.gateworks.com/gwsoc/ here]. |
| 63 | | |
| 64 | | '''Note''' The GW16113 is pre-programmed with all pins set to act as a GPIO / DIO. |
| 65 | | |
| 66 | | Users can also choose to customize the firmware on their own to suit their needs. The Gateworks PSoC Creator source is available [https://github.com/Gateworks/gwsoc here]. The [http://www.cypress.com/psoccreator/ Cypress PSoC Creator] is the free Windows development tool provided by Cypress used to design and compile firmware for PSoC devices. |
| 67 | | |
| 68 | | The GW16113 uses the [http://www.cypress.com/products/cy8c58lpxxx CY8C58LP] (part number: CY8C5888LTI-LP097) from the [http://www.cypress.com/products/psoc-5lp PSoC5LP family] which has the following: |
| 69 | | * 32bit ARM Cortex-M3 CPU with 32 interrupts |
| 70 | | * 24-channel DMA controller |
| 71 | | * 24-bit 64-tap fixed-point digital filter processor (DFB) |
| 72 | | * 256KB program flash |
| 73 | | * 64KB RAM |
| 74 | | * 2KB EEPROM |
| 75 | | * Digital peripherals: |
| 76 | | * 4x 16bit timer, counter and PWM blocks |
| 77 | | * 1x I2C controller (up to 1mbps speed) |
| 78 | | * 1x USB 2.0 Full-Speed (FS) (12mbps) '''(not available for use - this is how we communicate to the host processor)''' |
| 79 | | * 1x CAN 2.0b (16rx / 8tx bufers) |
| 80 | | * 20 to 24 universal digital blocks (UDB) programmable to create any number of functions: |
| 81 | | * 8-, 16-, 24-, and 32-bit timers, counters and PWMs |
| 82 | | * I2C, UART, SPI, I2S, LIN 2.0 interfaces |
| 83 | | * CRC blocks |
| 84 | | * Pseudo random sequence (PRS) generators |
| 85 | | * Quadrature decoders |
| 86 | | * Gate-level logic functions |
| 87 | | * Programmable clocking |
| 88 | | * Analog peripherals: |
| 89 | | * Configurable 8- to 20-bit delta-sigma ADC |
| 90 | | * 2x 12-bit SAR ADCs |
| 91 | | * 4x 8bit DACs |
| 92 | | * 4x comparators |
| 93 | | * 4x opamps |
| 94 | | * 4x programmable analog blocks to create: |
| 95 | | * Programmable gain amplifier (PGA) |
| 96 | | * Transimpedance amplifier (TIA) |
| 97 | | * Mixer |
| 98 | | * Sample and hold circuit |
| 99 | | * Cypress !CapSense support |
| 100 | | * 1.024V +/- 0.1% internal voltage reference |
| 101 | | * LCD direct drive from any GPIO |
| 102 | | |
| 103 | | References: |
| 104 | | * [http://www.gateworks.com/product/item/ventana-gw16113-expansion-adapter GW16113 Product Page] |
| 105 | | |
| 106 | | === GW16113 JTAG Programming |
| 107 | | If you are going to develop your own firmware for PSoC on the GW16113 you need the following: |
| 108 | | * [http://www.cypress.com/documentation/development-kitsboards/cy8ckit-002-psoc-miniprog3-program-and-debug-kit Cypress MiniProg3] Programming kit |
| 109 | | * GW16115 Carrier - provides 10-pin JTAG header on the GW16113 via pogo-pins |
| 110 | | [[Image(1611516113.jpg,300px)]] |
| 111 | | [[Image(cypress16115.jpg,300px)]] |
| 112 | | |
| 113 | | To program or recover a PSoC on the GW16113 you need to program it via JTAG which requires a GW16115 USB carrier that has pogo-pins to mate with the GW16113's JTAG pins. There are two methods involving different versions of the GW16115: |
| 114 | | - GW16115 pogo-pin adapter with resistor loading for the J1 Cypress 10-pin JTAG header with the Cypress miniProg programmer hardware/software and a .hex file |
| 115 | | - GW16115 pogo-pin adapter with resistor loading for the J2 Gateworks 10-pin JTAG header with a Gatworks JTAG dongle or gang programmer and a .xsvf file |
| 116 | | |
| 117 | | The Cypress PSoC Programmer application needs the following settings: |
| 118 | | - Open the 'hex' file with firmware you wish to program |
| 119 | | - Configure device family to: Cy8C5xxxLP |
| 120 | | - Configure device to: CY8C5888LTQ-LP097 |
| 121 | | - Verification: off |
| 122 | | - Autodetect: off |
| 123 | | - Protocol: SWD |
| 124 | | - Voltage: 3.3V |
| 125 | | |
| 126 | | Procedure: |
| 127 | | 1. Connect !MiniProg to Windows host PC |
| 128 | | 2. Connect !MiniProg 10-pin jtag cable to J1 on GW16115 wich GW16113 loaded (do not provide external power by connecting USB to a host) |
| 129 | | 3. Connect via the connect icon |
| 130 | | 4. Power via the power icon |
| 131 | | 5. Program via the run icon |
| 132 | | |
| 133 | | Notes: |
| 134 | | * Protocol of 5-wire JTAG will work as well and if 5-wire JTAG has been disabled via pin-config it silently falls back to SWD, so I find it better to just use SWD in the first place |
| 135 | | * Power on seems optional... it will eventually power the board on regardless |
| 136 | | |
| 137 | | |
| 138 | | [=#firmwareimages] |
| 139 | | === Firmware Images === |
| 140 | | The current firmware images available from Gateworks [http://dev.gateworks.com/gwsoc/ here] are: |
| 141 | | * GW16113_HID_GPIO - Vendor-ID/Product-ID: 0x2beb:0x1110 (all pins set to act as a GPIO / DIO) |
| 142 | | |
| 143 | | The firmware resides in the 256KB PSoC FLASH therefore is non-volatile and contains both the bootloader as well as the main application. See [#firmwareupdate below] regarding firmware updates. |
| 144 | | |
| 145 | | |
| 146 | | [=#firmwareupdate] |
| 147 | | === Firmware Updates === |
| 148 | | The PSoC has 256KB of programmable non-volatile FLASH that are used to contain the 'firmware application'. The pre-built firmware images provided by Gateworks contain a PSoC5 Bootloader application that allows for USB updates of the main application (aka bootloadable) firmware. |
| 149 | | |
| 150 | | GW16113 bootloader details: |
| 151 | | * Bootloader is programmed at the factory via JTAG and is not able to be updated via USB (technically an application firmware can be created that allows updating the bootloader however Gateworks does not currently support this) |
| 152 | | * USB Vendor-ID and Product-ID of bootloader: 0x2beb:0x1100 |
| 153 | | * Bootloader application is run when GW16113 comes out of reset (when PCI_RESET# is released) and will do one of the following depending on EEPROM configuration: |
| 154 | | 1. remain in the bootloader awaiting a command (to jump to existing app, or program new app) |
| 155 | | 2. remain in the bootloader awaiting a command if the state of the I/O ports latched coming out of reset matches a predefined value, otherwise jump to the application immediately |
| 156 | | 3. jump directly to application |
| 157 | | * main application can be instructed to jump to the bootloader and wait for a command (to allow firmware updating) |
| 158 | | |
| 159 | | Options 1 and 2 above are designed to provide a fool-proof way of recovering from a failed firmware update, or faulty firmware that does not allow a method to jump back to the bootloader. |
| 160 | | |
| 161 | | The factory default configuration is to stay in the bootloader a logic value of 0x55 (pin1,3,5,7 logic high, pin2,4,6,8 logic low) is latched on P12 (J1) when the GW16113 comes out of reset (option 2 above). |
| 162 | | |
| 163 | | The bootloader configuration is stored in the PSoC EEPROM and can be altered via the [#gwsoc gwsoc] application (or directly by the main application if using custom firmware) if the default configuration does not suit your needs. |
| 164 | | |
| 165 | | The [#gwsoc gwsoc] application running on the host processor has the ability to instruct the application to jump to the bootloader and await a command for updating the main application firmware. The '-p' command-line option is used to update the firmware providing a '.cyacd' file. |
| 166 | | |
| 167 | | Examples: |
| 168 | | * program GW16113_HID-GPIO firmware: |
| 169 | | {{{ |
| 170 | | wget http://dev.gateworks.com/gwsoc/gw16113/GW16113_HID-GPIO.cyacd |
| 171 | | gwsoc -p GW16113_HID-GPIO.cyacd |
| 172 | | }}} |
| 173 | | |
| 174 | | If for some reason the use case demands the 15KB FLASH space (of 256KB available) used by the bootloader or the ability to update the firmware via USB is not desired, the firmware can be customized by the user to eliminate the bootloader. The resulting firmware would need to be programmed via JTAG. Contact sales@gateworks.com if this is a requirement. |
| 175 | | {{{ |
| 176 | | #!comment References: |
| 177 | | * [file:///home/tharvey/Downloads/Bootloadable_Bootloader_001-92648.pdf Bootloader and Bootloadable Component Datasheet] |
| 178 | | }}} |
| | 51 | == Cable and Connector Information == |
| | 52 | Cables are sold separately. |
| | 53 | |
| | 54 | [wiki:alternateconnectors#GW16113ExpansionCardCableInformation Please see information here] |
| | 55 | |
| | 56 | |
| 206 | | === Universal Asynchronous Receiver Transmitter (UART) === |
| 207 | | The [http://www.cypress.com/documentation/component-datasheets/software-transmit-uart-swtxuart?source=search&keywords=uart&cat=software_tools Universal Asynchronous Receiver Transmitter (UART) Component] Features |
| 208 | | * 9-bit address mode with hardware address detection |
| 209 | | * Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps |
| 210 | | * RX and TX buffers = 4 to 65535 |
| 211 | | * Detection of Framing, Parity, and Overrun errors |
| 212 | | * Full Duplex, Half Duplex, TX only, and RX only optimized hardware |
| 213 | | * Two out of three voting per bit |
| 214 | | * Break signal generation and detection |
| 215 | | * 8x or 16x oversampling |
| 216 | | |
| 217 | | The PSoC 5LP does not have fixed hardware UART blocks but instead uses resources from the UDB array. |
| 218 | | |
| 219 | | The USB API will allow the following: |
| 220 | | * read/write data |
| 221 | | * configure data communications |
| 222 | | |
| 223 | | Note that there are no transceivers on the GW16113 therefore all signalling is 3.3V TTL level and if RS232 signalling is necessary an RS232 transceiver would be needed off-board. |
| 224 | | |
| 225 | | Reference: |
| 226 | | * [http://www.cypress.com/file/177171/download UART component datasheet] |
| 227 | | |
| 228 | | |
| 229 | | |
| 230 | | === I2C Interface === |
| 231 | | The [http://www.cypress.com/documentation/component-datasheets/i2c-mastermulti-masterslave?source=search&keywords=i2c&cat=software_tools I2C component] supports I2C slave, master, and multi-master configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. |
| 232 | | |
| 233 | | The I2C component supports standard clock speeds up to 1mbps and is compatible with I2C standard mode, fast mode, and fast mode plus devices as defines in the NXP I2C-bus specification. |
| 234 | | |
| 235 | | Features: |
| 236 | | * supports slave / master / multi-master and multi-master-slave operation |
| 237 | | * 2 pin standard I^2^C bus |
| 238 | | * supports standard data rates of 100 / 400 / 1000kbps |
| 239 | | |
| 240 | | The PSoC 5LP has 1 fixed hardware I2C block and can provide additional I2C components via UDB blocks. |
| 241 | | |
| 242 | | The USB API will allow the following: |
| 243 | | * read/write data |
| 244 | | * configure data communications |
| 245 | | |
| 246 | | |
| 247 | | Reference: |
| 248 | | * [http://www.cypress.com/file/175671/download I2C component datasheet] |
| 249 | | |
| 250 | | |
| 251 | | === Serial Peripheral Interface (SPI) === |
| 252 | | The [http://www.cypress.com/documentation/component-datasheets/serial-peripheral-interface-spi-master?source=search&keywords=spi&cat=software_tools Serial Peripheral Interface (SPI) Master component] features: |
| 253 | | * 3 to 16bit data width |
| 254 | | * four SPI operation modes |
| 255 | | * bitrate up to 18mbps |
| 256 | | |
| 257 | | The PSoC 5LP does not have a fixed hardware SPI master interface but instead uses resources from the UDB array. There is both a SPI Master component and SPI Slave component available but the default configuration for the GW16113 will support the master. |
| 258 | | |
| 259 | | The USB API will allow the following: |
| 260 | | * read/write data |
| 261 | | * configure data communications |
| 262 | | |
| 263 | | Reference: |
| 264 | | * [http://www.cypress.com/file/135226/download SPI Master component datasheet] |
| 265 | | |
| 266 | | |
| 267 | | === Controller Area Network (CAN) === |
| 268 | | The [http://www.cypress.com/documentation/component-datasheets/controller-area-network-can?source=search&keywords=can&cat=software_tools Controller Area Network component] has the following features: |
| 269 | | * CAN2.0A and CAN2.0B protocol implementation, ISO 11898-1 compliant |
| 270 | | * Programmable bit rate up to 1 Mbps at 8 MHz (BUS_CLK) |
| 271 | | * Two-wire or three-wire interface to external transceiver (Tx, Rx, and Enable) |
| 272 | | * Extended hardware message filter that covers Data Byte 1 and Data Byte 2 fields |
| 273 | | * Programmable transmit priority: Round Robin and Fixed |
| 274 | | |
| 275 | | Note that the GW16113 does not have a CAN transceiver. The external pinout will be 3.3V TTL and a CAN transceiver and termination would need to be available off-board. |
| 276 | | |
| 277 | | The USB API will allow the following: |
| 278 | | * read/write data |
| 279 | | * configure data communications |
| 280 | | |
| 281 | | Reference: |
| 282 | | * [http://www.cypress.com/file/135116/download Controller Area Network component datasheet] |
| 283 | | |
| 284 | | |
| 285 | | === Delta Sigma Analog to Digital Converter (ADC_DelSig) === |
| 286 | | The [http://www.cypress.com/documentation/component-datasheets/delta-sigma-analog-digital-converter-adcdelsig?source=search&keywords=adc&cat=software_tools Delta Sigma Analog to Digital Converter (ADC_DelSig)] has the following features: |
| 287 | | * Selectable resolutions, 8 to 20 bits |
| 288 | | * Eleven input ranges for each resolution |
| 289 | | * Sample rate 8 sps to 384 ksps |
| 290 | | * Operational modes: |
| 291 | | * Single sample |
| 292 | | * Multi-sample |
| 293 | | * Continuous mode |
| 294 | | * Multi-sample (Turbo) |
| 295 | | * High input impedance input buffer |
| 296 | | * Selectable input buffer gain (1, 2, 4, 8) or input buffer bypass |
| 297 | | * Multiple internal or external reference options |
| 298 | | * Automatic power configuration |
| 299 | | * Up to four run-time ADC configurations |
| 300 | | |
| 301 | | The USB API will allow the following: |
| 302 | | * start/stop conversion |
| 303 | | * read ADC value |
| 304 | | * select input buffer gain |
| 305 | | |
| 306 | | Reference: |
| 307 | | * [http://www.cypress.com/file/135096/download Delta Sigma Analog to Digital Converter component datasheet] |
| 308 | | |
| 309 | | |
| 310 | | === Sequencing Successive Approximation ADC === |
| 311 | | The [http://www.cypress.com/documentation/component-datasheets/adc-successive-approximation-register-adcsar?source=search&keywords=adc&cat=software_tools Sequencing Successive Approximation (SAR) ADC component] provides a 12-bit successive approximation with conversions up to 1M samples per second and a signal to noise ratio better than 70dB. |
| 312 | | |
| 313 | | Features: |
| 314 | | * selectable resolution (8, 10, 12 bit) |
| 315 | | * selectable sample rate (up to 1 Msps) |
| 316 | | |
| 317 | | The USB API will allow the following: |
| 318 | | * start/stop conversion |
| 319 | | * read ADC value |
| 320 | | * configure resolution and samplerate |
| 321 | | |
| 322 | | Reference: |
| 323 | | * [http://www.cypress.com/file/135101/download Sequencing Successive Approximation (SAR) ADC component datasheet] |
| 324 | | |
| 325 | | |
| 326 | | === Digital to Analog Converter (DAC) === |
| 327 | | The [http://www.cypress.com/documentation/component-datasheets/8-bit-waveform-generator-wavedac8?source=search&keywords=dac&cat=software_tools 8-Bit Waveform Generator] features include: |
| 328 | | * Supports standard and arbitrary waveform generation or static voltage driven or current source/sink value |
| 329 | | * Arbitrary waveform may be drawn manually or imported from file |
| 330 | | * Output may be voltage or current, sink or source |
| 331 | | * Voltage output can be buffered or direct from DAC |
| 332 | | * Hardware selection between two waveforms |
| 333 | | * Waveforms may be up to 4000 points |
| 334 | | * Predefined sine, triangle, square, and sawtooth waveforms |
| 335 | | |
| 336 | | The USB API will allow the following: |
| 337 | | * start/stop output |
| 338 | | * configure waveform (with 4 to 4000 sample points) |
| 339 | | * configure drive mode and speed |
| 340 | | * select current or voltage mode |
| 341 | | |
| 342 | | Reference: |
| 343 | | * [http://www.cypress.com/file/135271/download 8-Bit Waveform Generator component datasheet] |
| 344 | | |
| 345 | | |
| 500 | | |
| 501 | | === PSoC Resources and Capabilities === |
| 502 | | Cypress provides pre-configured functional blocks referred to as 'Components' that can be supported by the PSoC. Conceptually these are '''virtual peripherals''' that each have their own datasheet, schematic library representation, and support code implementing an API. |
| 503 | | |
| 504 | | The [http://www.cypress.com/psoccreator/ Cypress PSoC Creator] is the free Windows development tool provided by Cypress used to design and compile firmware for PSoC devices. To create firmware that can be programmed on a PSoC you use this tool to drag-and-drop and configure schematic representations of components and edit ANSI-C code to configure and control the components. |
| 505 | | |
| 506 | | A list of components compatible with the PSoC 5LP is available from Cypress [http://www.cypress.com/search/all?f%5B0%5D=meta_type%3Asoftware_tools&f%5B1%5D=software_tools_meta_type%3A532 PSoC5LP here] and all of these are available within PSoC Creator. |
| 507 | | |
| 508 | | Each PSoC 5LP has a fixed set of internal resources available such as: |
| 509 | | * RAM |
| 510 | | * FLASH storage |
| 511 | | * Univeral Design Blocks (UDB) |
| 512 | | * Digital clock dividers |
| 513 | | * Pins |
| 514 | | * DMA channels |
| 515 | | * Comparators |
| 516 | | * Programmable Analog Blocks |
| 517 | | * Interrupts |
| 518 | | * various Fixed blocks (ie USB, CAN, I2C, SPI, UART, controllers) |
| 519 | | |
| 520 | | Each component has its own individual datasheet that contains details such as: |
| 521 | | * Features |
| 522 | | * Software API |
| 523 | | * Hardware configuration info |
| 524 | | * Resource usage |
| 525 | | |
| 526 | | To determine what can fit into a PSoC you can compare the PSoC datasheet list of resources with the individual component datasheets. Preferably PSoC Creator can generate a resource summary by: |
| 527 | | * Workspace Explorer -> Results Tab -> Select the usage report file titled <project-name>.rpt |
| 528 | | * Build -> Generate Project Datasheet (refer to section 2) |
| 529 | | |
| 530 | | Cypress also has a nifty online tool that knows quite a bit about what each component needs and what is available. It is used for selecting a PSoC chip but can also be useful to prove that your basic needs can be met. You can find their epsg tool [http://www.cypress.com/epsg/ here]. Note that this tool does not take into account that we only have 24 I/O pins available to connectors. |
| 531 | | |
| 532 | | References: |
| 533 | | * [http://www.cypress.com/search/all?f%5B0%5D=meta_type%3Asoftware_tools&f%5B1%5D=software_tools_meta_type%3A532 PSoC5LP Component Datasheets] |
| 545 | | == Cable and Connector Information == |
| 546 | | Cables are sold seperately. |
| 547 | | |
| 548 | | [wiki:alternateconnectors#GW16113ExpansionCardCableInformation Please see information here] |
| | 241 | |
| | 242 | == Firmware == |
| | 243 | Pre-built firmware configurations may be available for download [http://dev.gateworks.com/gwsoc/ here]. |
| | 244 | |
| | 245 | '''Note''' The GW16113 is pre-programmed with all pins set to act as a GPIO / DIO. |
| | 246 | |
| | 247 | |
| | 248 | The GW16113 uses the [http://www.cypress.com/products/cy8c58lpxxx CY8C58LP] (part number: CY8C5888LTI-LP097) from the [http://www.cypress.com/products/psoc-5lp PSoC5LP family] which has the following: |
| | 249 | * 32bit ARM Cortex-M3 CPU with 32 interrupts |
| | 250 | * 24-channel DMA controller |
| | 251 | * 24-bit 64-tap fixed-point digital filter processor (DFB) |
| | 252 | * 256KB program flash |
| | 253 | * 64KB RAM |
| | 254 | * 2KB EEPROM |
| | 255 | * Cypress !CapSense support |
| | 256 | * 1.024V +/- 0.1% internal voltage reference |
| | 257 | |
| | 258 | References: |
| | 259 | * [http://www.gateworks.com/product/item/ventana-gw16113-expansion-adapter GW16113 Product Page] |
| | 260 | |
| | 261 | |
| | 262 | |
| | 263 | [=#firmwareimages] |
| | 264 | === Firmware Images === |
| | 265 | The current firmware images available from Gateworks [http://dev.gateworks.com/gwsoc/ here] are: |
| | 266 | * GW16113_HID_GPIO - Vendor-ID/Product-ID: 0x2beb:0x1110 (all pins set to act as a GPIO / DIO) |
| | 267 | |
| | 268 | The firmware resides in the 256KB PSoC FLASH therefore is non-volatile and contains both the bootloader as well as the main application. See [#firmwareupdate below] regarding firmware updates. |
| | 269 | |
| | 270 | |
| | 271 | [=#firmwareupdate] |
| | 272 | === Firmware Updates === |
| | 273 | The PSoC has 256KB of programmable non-volatile FLASH that are used to contain the 'firmware application'. The pre-built firmware images provided by Gateworks contain a PSoC5 Bootloader application that allows for USB updates of the main application (aka bootloadable) firmware. |
| | 274 | |
| | 275 | GW16113 bootloader details: |
| | 276 | * Bootloader is programmed at the factory via JTAG and is not able to be updated via USB (technically an application firmware can be created that allows updating the bootloader however Gateworks does not currently support this) |
| | 277 | * USB Vendor-ID and Product-ID of bootloader: 0x2beb:0x1100 |
| | 278 | * Bootloader application is run when GW16113 comes out of reset (when PCI_RESET# is released) and will do one of the following depending on EEPROM configuration: |
| | 279 | 1. remain in the bootloader awaiting a command (to jump to existing app, or program new app) |
| | 280 | 2. remain in the bootloader awaiting a command if the state of the I/O ports latched coming out of reset matches a predefined value, otherwise jump to the application immediately |
| | 281 | 3. jump directly to application |
| | 282 | * main application can be instructed to jump to the bootloader and wait for a command (to allow firmware updating) |
| | 283 | |
| | 284 | Options 1 and 2 above are designed to provide a fool-proof way of recovering from a failed firmware update, or faulty firmware that does not allow a method to jump back to the bootloader. |
| | 285 | |
| | 286 | The factory default configuration is to stay in the bootloader a logic value of 0x55 (pin1,3,5,7 logic high, pin2,4,6,8 logic low) is latched on P12 (J1) when the GW16113 comes out of reset (option 2 above). |
| | 287 | |
| | 288 | The bootloader configuration is stored in the PSoC EEPROM and can be altered via the [#gwsoc gwsoc] application (or directly by the main application if using custom firmware) if the default configuration does not suit your needs. |
| | 289 | |
| | 290 | The [#gwsoc gwsoc] application running on the host processor has the ability to instruct the application to jump to the bootloader and await a command for updating the main application firmware. The '-p' command-line option is used to update the firmware providing a '.cyacd' file. |
| | 291 | |
| | 292 | Examples: |
| | 293 | * program GW16113_HID-GPIO firmware: |
| | 294 | {{{ |
| | 295 | wget http://dev.gateworks.com/gwsoc/gw16113/GW16113_HID-GPIO.cyacd |
| | 296 | gwsoc -p GW16113_HID-GPIO.cyacd |
| | 297 | }}} |
| | 298 | |
| | 299 | If for some reason the use case demands the 15KB FLASH space (of 256KB available) used by the bootloader or the ability to update the firmware via USB is not desired, the firmware can be customized by the user to eliminate the bootloader. The resulting firmware would need to be programmed via JTAG. Contact sales@gateworks.com if this is a requirement. |
| | 300 | {{{ |
| | 301 | #!comment References: |
| | 302 | * [file:///home/tharvey/Downloads/Bootloadable_Bootloader_001-92648.pdf Bootloader and Bootloadable Component Datasheet] |
| | 303 | }}} |
| | 304 | |
