Changes between Version 19 and Version 20 of faq


Ignore:
Timestamp:
08/09/2018 11:34:33 PM (15 months ago)
Author:
Tim Harvey
Comment:

remove avila/cambria/rincon data

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  • faq

    v19 v20  
    129129[=#pci]
    130130== What throughput does the PCIe lane support? ==
    131 Avila / Cambria / Laguna boards support PCI Gen1 which provides a maxium theoretical bus bandwidth of 2.5Gbits/sec.
     131Laguna boards support PCI Gen1 which provides a maxium theoretical bus bandwidth of 2.5Gbits/sec.
    132132
    133133Ventana boards support PCI Gen1 due to early revisions of the boards not having an PCIe Gen2 external clock generator. Certain board revisions with an external clock generator can technically support Gen2 if it is enabled in software. See [wiki:ventana/PCIe] for more details.