Laguna L2 Cache Performance

The cns3xxx processor family contains a L2X0 cache controller implementing a Level 2 CPU cache. This can be enabled in the Linux kernel via the CONFIG_CACHE_L2X0 kernel configuration and is generally enabled by default.

L2 Cache provides a significant performance benefit for CPU bound operations (ie software compression/decrompression or encryption/decryption) however provides a performance hit for I/O bound operations (ie bridging and stateless routing).

Depending on your application you will want to experiment to see which settings provides the best benefit. If you're implementing a network bridge for example, you will want L2X0 disabled for a 60% improvement increase over it being enabled. The opposite is true for CPU intensive operations. For a task which may involve both experimentation is needed.

13.06+ OpenWrt BSP (3.x kernel)

If using our software BSP 13.06 or greater the kernel commandline 'nol2x0' has been added to allow you to disable L2X0 at boot-time dynamically such that you do not have to rebuild the kernel.

For example, you can do this in uboot:

Laguna > print bootargs
bootargs=console=ttyS0,115200 root=/dev/mtdblock3 rootfstype=squashfs,jffs2
Laguna > setenv bootargs console=ttyS0,115200 root=/dev/mtdblock3 rootfstype=squashfs,jffs2 nol2x0
Laguna > saveenv

12-10 OpenWrt BSP (2.6.39 kernel)

The default firmware builds the kernel with L2X0 disabled.

To change this configuration use the 'make kernel_menuconfig' make target in the OpenWrt buildroot directory and select or de-select 'System Type'->'Enable the L2x0 outer cache controller'

Last modified 5 years ago Last modified on 10/22/2017 05:28:45 AM