| | 1 | [[PageOutline]] |
| | 2 | |
| | 3 | = Newport Digital IO |
| | 4 | The intent of this page is to provide information about Newport single board computers off-board digital IO signals. |
| | 5 | |
| | 6 | == DIO Mapping |
| | 7 | Newport baseboards provide 4 digital IO signals to an off-board connector. The CN81XX has a single GPIO blocks having 48 GPIO's. Note that only 32 of these are accessible on the CN80XX used on Newport boards. Each GPIO controller gets mapped to a range of Linux gpio's by the Linux kernel. Note that this mapping is not guaranteed to stay the same across kernel versions - you can look at the debugfs {{{/sys/kernel/debug/gpio}}} file to see where the GPIO controllers are mapped. |
| | 8 | |
| | 9 | The various Newport product hardware manuals contain a table of what pins on the Digital IO connector routes to what CN80XX GPIO. For convenience this information is also provided in the table below. |
| | 10 | |
| | 11 | Note that all four DIO signals contain an internal weak pulldown approximately 50kohm. |
| | 12 | |
| | 13 | Newport GPIO Mapping: |
| | 14 | ||= Board =||= DIO^^^1^^^ =||= Connector^^^2^^^ =||= CN80XX GPIO^^^3^^^ =||= Linux gpio ^^^4^^^ =||= Termination^^^5^^^ || Notes^^^6^^^ =|| |
| | 15 | || GW640x || DIO0 || J15.1 || GPIO_24 || gpio-464 || RC/TVS termination || || |
| | 16 | || || DIO1 || J15.2 || GPIO_25 || gpio-465 || RC/TVS termination || || |
| | 17 | || || DIO2 || J15.3 || GPIO_26 || gpio-466 || RC/TVS termination || || |
| | 18 | || || DIO3 || J15.4 || GPIO_27 || gpio-467 || RC/TVS termination || build option exists to route to a 0-5V ADC || |
| | 19 | || || GND || J15.5 || - || - || || || |
| | 20 | |||| |
| | 21 | || GW630x || DIO0 || J13.1 || GPIO_24 || gpio-464 || RC/TVS termination || || |
| | 22 | || || DIO1 || J13.2 || GPIO_25 || gpio-465 || RC/TVS termination || || |
| | 23 | || || DIO2 || J13.3 || GPIO_26 || gpio-466 || RC/TVS termination || || |
| | 24 | || || DIO3 || J13.4 || GPIO_27 || gpio-467 || RC/TVS termination || build option exists to route to a 0-5V ADC || |
| | 25 | || || GND || J13.5 || - || - || || || |
| | 26 | |||| |
| | 27 | || GW620x || DIO0 || J10.1 || GPIO_24 || gpio-464 || RC/TVS termination || || |
| | 28 | || || DIO1 || J10.2 || GPIO_25 || gpio-465 || RC/TVS termination || || |
| | 29 | || || DIO2 || J10.3 || GPIO_26 || gpio-466 || RC/TVS termination || build option exists to route to a 0-5V ADC || |
| | 30 | || || DIO3 || J10.4 || GPIO_27 || gpio-467 || RC/TVS termination || build option exists to route to GSC User PB or Tamper || |
| | 31 | || || GND || J10.5 || - || - || || || |
| | 32 | || || VDD_3P3 || J10.6 || - || - || - || 1.0Amax; build option exists to route to VDD_5P0 || |
| | 33 | |||| |
| | 34 | || GW610x || DIO0 || J10.19 || GPIO_24 || gpio-464 || R termination || || |
| | 35 | || || DIO1 || J10.20 || GPIO_25 || gpio-465 || R termination || || |
| | 36 | || || DIO2 || J10.17 || GPIO_26 || gpio-466 || R termination || || |
| | 37 | || || DIO3 || J10.18 || GPIO_27 || gpio-467 || R termination || || |
| | 38 | || || GND || J10.2/4/6 || - || - || || || |
| | 39 | || || VDD_3P3 || J10.1/3 || - || - || || 1.0A max || |
| | 40 | || || VDD_5P0 || J10.5 || - || - || || 1.0A max || |
| | 41 | 1. This is the signal name from the Newport hardware manuals |
| | 42 | 2. This is the connector pinout |
| | 43 | 3. This is the GPIO as seen by the CN80XX |
| | 44 | 4. This is the gpio mapped in linux accessible via {{{/sys/class/gpio}}}. Note that you will have to manually export these (see [wiki:gpio]) |
| | 45 | 5. Electrical termination includes an internal ~50kohm weak pull-down as well as the following if specified: |
| | 46 | * '''RC''' consists of a 330ohm series current limit resistor and a 390pF cap to GND |
| | 47 | * '''R''' consists of a 330ohm series current limit resistor |
| | 48 | * '''TVS''' consists of a 5V-3.5PF IEC6100042 Transient Voltage Suppression diode |
| | 49 | 6. Build options if specified requires a Gateworks Special - contacts sales@gateworks.com for details |
| | 50 | |
| | 51 | |
| | 52 | = Software GPIO Configuration |
| | 53 | Each CN80XX GPIO can be pin-muxed to a variety of functions internal to the SoC including software controlled GPIO function (default), clock outputs, PTP (packet timestamp) outputs, UART TX/RX/DTR/RTS, SATA activity LED, additional SPI chip selects. For more detail on this, consult the [http://github.com/Gateworks/bdk-newport Cavium Board Diagnostics Kit source code] and/or the Cavium CN80XX Hardware Manual (obtained from Cavium under NDA). |
| | 54 | |
| | 55 | Please visit this link to find out more information about using GPIO's in Linux |
| | 56 | * [wiki:gpio GPIO basics and Linux configuration] |
| | 57 | |
| | 58 | |
| | 59 | = Configuring GPIO Hardware |
| | 60 | The CN80XX GPIO signals do not have the ability to configure their drive strength or other I/O characteristics. |
