Changes between Version 15 and Version 16 of newport/errata

03/25/2022 10:44:57 PM (15 months ago)
Tim Harvey

added GPY111 PHY errata


  • newport/errata

    v15 v16  
    197197 * GSC firmware v60
     202== NP12 GPY111 PHY replacement
     204 * Due to supply chain limitations the DP83867 GbE PHY has been replaced with the GPY111 GbE PHY
     207 * Software support already present in the latest Newport Gateworks boot firmware is needed to support this PHY. If using older boot firmware the following patches are needed:
     208  - BDK:
     209   * [ newport: change GW620x-D+ phy-reset polarity] (for GW620x)
     210   * [ newport: change GW630x-F.1+ phy-reset polarity] (for GW630x)
     211   * [ newport: store PHY config in dt for U-Boot/Linux PHY drivers]
     212   * [ newport: add display for MaxLinear GPY111 PHY]
     213  - U-Boot:
     214   * [ net: octontx: xcv: set RGMII drive compensation via dt props]
     215   * [ net: phy: do not soft reset PHY by default]
     217Affected Products:
     218 - GW630x-F+ (PCB 02210153-05)
     219 - GW620x-D+ (PCB 02210152-03)
     222 - If your software has the required support the PHY will be shown in BDK as follows:
     224MDIO0 : GPY111 (RGMII)
     225MDIO1 : GPY111 (SGMII)
     227 - If you are missing the required support you will see:
     229MDIO0  : error: 0xffff
     230MDIO1  : error: 0xffff
     235== NP13 GPY111 PHY bit error rate and link errata
     238 * The GPY111 PHY used on a variety of boards in the Venice product family has some errata from the manufacturer that affects Newport products:
     239  1. When operating on a GbE link occasionally a link will have a high CRC error rate directly after a cable plug-in or board power-up event. A link down/up event will typically resolve this issue.
     240  2. Rare link failure between MAC and PHY in SGMII mode: The GW630x/GW602x eth0 MAC uses SGMII bus signalling and in rare occasions a link failure occurs between the MAC and PHY which will result in a "BGX AN_CPT not completed" message from the U-Boot / Linux BGX driver and a non-functioning eth0 device.
     243 - Issue #1 is addressed internally by firmware in the PHY: If the PHY exceeds an allowed threshold of 'Start-of-Stream Delimiter' (SSD) errors it will restart link negotiation a number of times before finally giving up and will then 'Auto-Downspeed' (ADS) to a 100mbps link. This feature is configured by the PHY LSADS field (bit 15 - 14) of the PHY_PHYCTL2 MII register (0x14) where a value of 00b is Off (ADS disabled), 01B will retry 1 time, 10B will retry 3 times (default), and 11B will retry 4 times. An ADS event is signaled by the LSADS bit (bit 8) of the PHY_PHYSTAT1 (0x11) MII register being set. The overall affect of using ADS is that the link may not be stable until it has settled after the link is brought up and in rare cases the link may settle at 100mbps. In extensive testing it has been found that link retries occurs about 1 in 100 plug-in/power-up events, an Auto-Downspeed to 100m occurs less than 1 in 5000 plug-in/power-up events, and that the link is stable within 30 seconds.
     244 - Issue #2 is only applicable to Newport GW630x/GW620x eth0 SGMII devices and is addressed by the bootloader detecting the issue and using the GSC to power cycle the board via a [ U-Boot patch]. If this occurs you will see the following message prior to your board power cycling automatically:
     246BGX AN_CPT not completed for SGMII link
     247resetting ...
     250Affected Products:
     251 - GW650x-A+ (PCB 02210330-00)
     252 - GW630x-F+ (PCB 02210153-05)
     253 - GW620x-D+ (PCB 02210152-03)