[[PageOutline]] = Newport Errata The below errata only affects certain models and certain revisions. Please contact support@gateworks.com with any questions. [=#np1] == NP1 Occasional failure to detect GigE PHY on GW6300-B Issue: * The TI DP83867 PHY's are occasionally not detected on board power-up. This is caused by the MDIO voltage rail inappropriately tied to 3.3V instead of the desired 2.5V as well as the lack of a RST# signal going to the PHY's which should not be necessary per the datasheet but has been found experimentally to be required. Upon failure the Boot Firmware will fail to detect the PHY on the MDIO channel and the network device will not be present. Resolution: * This is resolved on PCB 02210153-02 (GW630x-C) (Rev C) * This is resolved via re-work (cut/wire) on GW630x-B.3 (Rev B.3) Affected Product: * GW630x-B (PCB 02210153-01) [=#np2] == NP2 Reverse Polarity voltage protection Issue: * Reverse Polarity voltage protection on the power input to the board is not available. Powering the board with Vin polarity reversed will result in board damage. Resolution: * Reverse Polarity voltage protection will be added. Affected Product: * GW640x-A (PCB 02210154-00) * GW630x-B/C (PCB 02210153-01, PCB 02210153-02) * GW610x-A (PCB 02210151-00) Fixed in: * GW640x-B (PCB 02210154-01) * GW630x-D (PCB 02210153-03) * GW610x-B (PCB 02210151-01) [=#np3] == NP3 CPU Temperature Sensor Issue: * The temperature sense logic of the CN80XX Voltage Regulator Module (VRM) is not properly calibrated resulting in unexpected temperature readings (Cavium CN80XX ID 32702). As a result, the CPU Temperature is not obtainable from the SoC in current silicon (Pass 1.0, 1.1, 1.2) Resolution: * An external temperature sensing device will be added using the CN80XX thermal core diode junction to provide CPU temperature sense capability. Affected Product: * GW640x-A (PCB 02210154-00) * GW630x-B/C (PCB 02210153-01, PCB 02210153-01) Added in: * GW640x-B (PCB 02210154-01) * GW630x-D (PCB 02210153-03) [=#np4] == NP4 eFUSE Program-ability Issue: * The One-Time-Programmable (OTP) eFUSE banks available on the CN80XX require external circuitry to program. Resolution: * External circuitry will be added to boards to allow programming outside of a test fixture. Affected Product: * GW640x-A (PCB 02210154-00) * GW630x-B/C (PCB 02210153-01, PCB 02210153-01) Added in: * GW640x-B (PCB 02210154-01) * GW630x-D (PCB 02210153-03) [=#np5] == NP5 Fan Tachometer improvements Issue: * Certain fans either drive the TACH signal to an inappropriate voltage level for the GSC or produce too much of a load for the GSC to accurately measure TACH pulses. Resolution: * A FET added to the TACH signal provides voltage protection and isolates the load of the fan allowing the GSC to properly count TACH pulses. The TACH drive on the fan must be capable of sinking 5mA of current to assert the pulse to the GSC. Affected Product: * GW640x-A (PCB 02210154-00) * GW630x-B/C/D (PCB 02210153-01, PCB 02210153-02, PCB 02210153-03) * GW610x-A (PCB 02210151-00) Resolved in: * GW640x-B (PCB 02210154-01) * GW630x-E (PCB 02210153-04) * GW620x-A (PCB 02210152-00) * GW610x-B (PCB 02210151-00) [=#np6] == NP6 GW640x Ethernet LED's non-functional Issue: * The GW640x QSGMII ports do not have their RJ45 (J22) and SFP jack (J13) LED's connected properly. The RJ45 LED's will never illuminate and the SFP LED's will behave inconsistently. The RGMII LED's on J21 are connected and do behave as designed. Resolution: * Network connector LEDs are fixed on future board revision Affected Product: * GW640x-A (PCB 02210154-00) Fixed in: * GW640x-B (PCB 02210154-01) [=#np7] == NP7 CAN not functional Issue: * The CAN transceiver is missing a pull-down on its STBY signal rendering it unable to send/recv. Resolution: * Properly terminate the STBY signal Affected Product: * GW6404-A (PCB 02210154-00) * GW6304-A/B/C/D (PCB 02210153-00, PCB 02210153-01, PCB 02210153-02, PCB 02210153-03) * GW6204-A (PCB 02210152-00) Fixed in: * GW6404-B.1 (PCB 02210154-01) * GW6304-E (PCB 02210153-04) * GW6204-B (PCB 02210152-01) [=#np8] == NP8 GSC RTC Drift Issue: * The GSC may experience oscillator faults which cause RTC resets drift over time. Resolution: * Upgrade to the [wiki:gsc#GSCUpdates latest GSC firmware] (v55 or greater) to eliminate the GSC resets. * The GSC crystal and capacitors have been updated to resolve the oscillator faults and greatly reduce RTC drift. Affected Product: * GW610x-A/B (PCB 02210151-00, PCB 02210151-01) * GW620x-A/B (PCB 02210152-00, PCB 02210152-01) * GW630x-B/C/D/E (PCB 02210153-01, PCB 02210153-02, PCB 02210153-03, PCB 02210153-04) * GW640x-A/B (PCB 02210154-00, PCB 02210154-01) Added in: * GW610x-B.1 (PCB 02210151-01) * GW620x-B.1 (PCB 02210151-01) * GW630x-C.2/D.3/E.1 (PCB 02210153-02, PCB 02210153-03, PCB 02210153-04) * GW640x-B.1 (PCB 02210151-01) [=#np9] == NP9 Reverse Current Susceptibility Issue: * While 'reverse polarity' protection exists on most Gateworks boards allowing Vin polarity reversal to not damage boards, 'reverse current' protection does not exist on certain boards which could cause board damage under specific situations. A condition which would allow for such damage is if a board was connected to a Power-Over-Ethernet supply (regardless of if it is enabled for Active PoE) as well as at the same time powered with a lower voltage supply connected to board input power (ie barrel jack or 2-pin Vin aux connector). For example powering a board with 48V PoE at the same time as a 24V supply on the barrel jack would cause power to flow from the higher PoE positive rail back through the supply connected to the barrel jack which could put the supply in an over-current failure mode that sinks current directly to ground damaging the Gateworks board. Resolution: * Do not connect Ethernet PoE and the DC Power input (barrel jack or header) at the same time. Affected Products: * GW6905-A (PCB 02210207-00) * GW6904-A (PCB 02210206-00) * GW6902-A (PCB 02210209-00) * GW640x-A/B/C (PCB 02210154-00, 02210154-01, 02210154-02) * GW630x-A/B/C/D/E (PCB 02210153-00, 02210153-01, 02210153-02, 02210153-03, 02210153-04) * GW620x-A/B (PCB 02210152-00, 02210152-01) [=#np10] == NP10 GW6903 Front Panel LED Illumination Date: * 03/15/2020 Issue: * The Tri-Color Front Panel Red LED will always dimly illuminate, even when turned off via GPIO. Affected Products: * GW6903-A/B/B.1 (PCB 02210205-00, 02210205-01) [=#np11] == NP11: GSC lockup Issue: * An errata in the MSP430FR5847 used as the GSC (GSCv3) for Newport single board computers can cause unexpected GSC lockup events. The effects of a GSC lockup can be described as: - failure of board to boot due to inability to read board I2C EEPROM - failure to read the I2C RTC and update the system time - loss of RTC and GSC register configuration Affected Product: * GW6xxx Resolution: * Update boards to GSC firmware v60 Fixed in: * GSC firmware v60 [=#np12] == NP12 GPY111 PHY replacement Issue: * Due to supply chain limitations the DP83867 GbE PHY has been replaced with the GPY111 GbE PHY Resolution: * Software support already present in the latest Newport Gateworks boot firmware is needed to support this PHY. If using older boot firmware the following patches are needed: - BDK: * [https://github.com/Gateworks/bdk-newport/commit/83e317c45143ca041dfe95b37a197dd79210724e newport: change GW620x-D+ phy-reset polarity] (for GW620x) * [https://github.com/Gateworks/bdk-newport/commit/b19b8bdca7101b9cff9b2d0782c58360f97e35af newport: change GW630x-F.1+ phy-reset polarity] (for GW630x) * [https://github.com/Gateworks/bdk-newport/commit/97b95939e16427dee68d7bb3814620bd92034b8a newport: store PHY config in dt for U-Boot/Linux PHY drivers] * [https://github.com/Gateworks/bdk-newport/commit/7c4f88862b6416d008ed30635c6633f3161cd964 newport: add display for MaxLinear GPY111 PHY] - U-Boot: * [https://github.com/Gateworks/uboot-newport/commit/4676fabbbd4724976e99fb54ac4aaa27e4830c29 net: octontx: xcv: set RGMII drive compensation via dt props] * [https://github.com/Gateworks/uboot-newport/commit/ba68b943e3da2ab5382017f34b5e42bfc9ebfdda net: phy: do not soft reset PHY by default] - Linux: * No changes are necessary to the Linux kernel as long as you are not using the kernel driver intended for this PHY; CONFIG_INTEL_XWAY_PHY / drivers/net/phy/intel-xway.c; This driver may unintentionally reset the PHY and disturb the proper RGMII internal delays and/or LED functionality - do not use this driver by disabling it (CONFIG_INTEL_XWAY_PHY=n or blacklisting/removing the module) Affected Products: - GW630x-F+ (PCB 02210153-05) - GW620x-D+ (PCB 02210152-03) - GW6903-D+ (PCB 02210205-03) Notes: - If your software has the required support the PHY will be shown in BDK as follows: {{{ MDIO0 : GPY111 (RGMII) MDIO1 : GPY111 (SGMII) }}} - If you are missing the required support you will see: {{{ MDIO0 : error: 0xffff MDIO1 : error: 0xffff }}} [=#np13] == NP13 GPY111 PHY bit error rate and link errata Issue: * The GPY111 PHY used on a variety of boards in the Venice product family has some errata from the manufacturer that affects Newport products: 1. When operating on a GbE link occasionally a link will have a high CRC error rate directly after a cable plug-in or board power-up event. A link down/up event will typically resolve this issue. 2. Rare link failure between MAC and PHY in SGMII mode: The GW630x/GW602x eth0 MAC uses SGMII bus signalling and in rare occasions a link failure occurs between the MAC and PHY which will result in a "BGX AN_CPT not completed" message from the U-Boot / Linux BGX driver and a non-functioning eth0 device. Resolution: - Issue #1 is addressed internally by firmware in the PHY: If the PHY exceeds an allowed threshold of 'Start-of-Stream Delimiter' (SSD) errors it will restart link negotiation a number of times before finally giving up and will then 'Auto-Downspeed' (ADS) to a 100mbps link. This feature is configured by the PHY LSADS field (bit 15 - 14) of the PHY_PHYCTL2 MII register (0x14) where a value of 00b is Off (ADS disabled), 01B will retry 1 time, 10B will retry 3 times (default), and 11B will retry 4 times. An ADS event is signaled by the LSADS bit (bit 8) of the PHY_PHYSTAT1 (0x11) MII register being set. The overall affect of using ADS is that the link may not be stable until it has settled after the link is brought up and in rare cases the link may settle at 100mbps. In extensive testing it has been found that link retries occurs about 1 in 100 plug-in/power-up events, an Auto-Downspeed to 100m occurs less than 1 in 5000 plug-in/power-up events, and that the link is stable within 30 seconds. - Issue #2 is only applicable to Newport GW630x/GW620x eth0 SGMII devices and is addressed by the bootloader detecting the issue and using the GSC to power cycle the board via a [https://github.com/Gateworks/uboot-newport/commit/ab9de41855fde6a1393449e8af9a7d6381a01427 U-Boot patch]. If this occurs you will see the following message prior to your board power cycling automatically: {{{ BGX AN_CPT not completed for SGMII link resetting ... }}} Affected Products: - GW650x-A+ (PCB 02210330-00) - GW630x-F+ (PCB 02210153-05) - GW620x-D+ (PCB 02210152-03) - GW6903-D+ (PCB 02210205-03) [=#np14] == NP14 GPY111 limited ESD protection Issue:  * The GPY111 PHY used on a variety of boards lacks internal ESD protection to the level of modern standards which could result in network functionality being permanently limited due to ESD cable hot-plug events. Workaround: * For outdoor applications and boards that could be exposed to electrical events, we would recommend you use an external RJ45 surge protector. The following product also additionally helps to protect against lightning events up to IEC 61000-4-5 (Lightning) 40A (8/20us): - [http://datasheet.watchfuleyesolutions.com/US121101.html Watchful Eye WTH-SG/RJ45-S, US121101X] (Also available on Amazon) Resolution:  - additional ESD protection has been added between the GPY111 PHY and magnetics to the RJ45 Affected Products:  - GW620x-D (PCB 02210152-03)  - GW630x-F (PCB 02210153-05)  - GW650x-A (PCB 02210330-00) Resolved on:  - GW620x-E (PCB 02210152-04)  - GW630x-G (PCB 02210153-06)  - GW650x-B (PCB 02210330-01)