| 336 | | [=#firmware] |
| 337 | | = Boot Firmware (Up to and including the Bootloader) = |
| 338 | | The 'Boot Firmware' for Newport is defined as the combination of the First level 'boot stub' and the additional firmware stages through the bootloader. This can be broken down into the following stages: |
| 339 | | * Boot ROM (internal on CN80XX/CN81XX SoC): fetch first level boot stub (192KB limit) from boot device (MMC or SPI FLASH) |
| 340 | | * SPL (Secondary Program Loader) |
| 341 | | * Bootloader (U-Boot) |
| 342 | | |
| 343 | | For a Secondary Program Loader, or SPL, Gateworks currently uses the Cavium Board Development Kit (BDK) provided by their OCTEON-TX Software Development Kit (SDK). In this current implementation the Boot ROM loads and executes the BDK, the BDK loads and executes the ARM Trusted Firmware (ATF) and the ATF loads and executes the U-Boot bootloader in multiple stages as such: |
| 344 | | * First level: Bootstub (firmware/bdk) |
| 345 | | * Second level: ATF (firmware/atf) |
| 346 | | * Third level: U-Boot (bootloader/u-boot) |
| 347 | | |
| 348 | | Gateworks provides a pre-built Boot Firmware (firmware-newport.img) ready to flash onto boot devices as well as source for building and/or modifying the boot firmware yourself. |
| 349 | | |
| 350 | | |
| 351 | | [=#bootrom] |
| 352 | | == Boot ROM == |
| 353 | | The OCTEON-TX Boot ROM code loads an image from the primary boot device which can be either MMC or SPI FLASH. For a description of available boot devices see [#bootdevice below]. |
| 354 | | |
| 355 | | The Boot ROM uses information from 0x10000 to 0x7FFFF on the primary boot device. The first 64KB is not used by the Boot ROM and is used as a standard partition table for backwards compatibility with standard Operating Systems and from 0x80000 (512KB) onward is used by the Operating System. |
| 356 | | |
| 357 | | |
| 413 | | |
| 414 | | |
| 415 | | |
| 416 | | |
| 417 | | |
| 418 | | [=#bootloader] |
| 419 | | == U-Boot Bootloader == |
| 420 | | Gateworks supports the U-Boot Bootloader for the Newport product family. We provide pre-built firmware images (see [#firmware above) as well as source for building and/or modifying it yourself. |
| 421 | | |
| 422 | | One of the primary features of the Bootloader is to provide access to the {{{hwconfig}}} environment variable that the firmware uses for initial board configuration on power-up. |
| 423 | | |
| 424 | | [=#hwconfig] |
| 425 | | === hwconfig === |
| 426 | | The U-Boot Bootloader by convention provides a {{{hwconfig}}} environment variable which is used by the boot firmware (before U-Boot is loaded and executed) to configure board options at power-up. These options can include things such as: |
| 427 | | * miniPCIe socket functions (ie PCIe vs mSATA vs USB3.0) |
| 428 | | * serial configuration (ie RS232 vs RS485) |
| 429 | | |
| 430 | | [=#socketconfig] |
| 431 | | ==== hwconfig: miniPCIe Socket Configuration ==== |
| 432 | | Newport board model socket options: |
| 433 | | * GW630x: |
| 434 | | - J9: PCIe |
| 435 | | - J10: PCIe or SATA |
| 436 | | - J11: PCIe or USB3.0 |
| 437 | | |
| 438 | | Note that USB2.0 is routed to all three miniPCIe sockets always but as USB3.0 shares signals with PCIe you must choose between PCIe and USB3 on sockets that support USB3. |
| 439 | | |
| 440 | | You can get/set the {{{hwconfig}}} variable within the U-Boot bootloader but you must reboot the board for it to take effect as the variable is acted upon in the Secondary Program Loader (SPL). |
| 441 | | |
| 442 | | Examples: |
| 443 | | * GW630x: |
| 444 | | - J10 PCIe, J11 PCIe (default) |
| 445 | | {{{#!bash |
| 446 | | setenv hwconfig 'j10:pcie;j11:pcie'; saveenv |
| 447 | | }}} |
| 448 | | - J10 mSATA, J11 USB3.0 |
| 449 | | {{{#!bash |
| 450 | | setenv hwconfig 'j10:sata;j11:usb3'; saveenv |
| 451 | | }}} |
| 452 | | - J9/J10 disabled, J11 PCIe |
| 453 | | {{{#!bash |
| 454 | | setenv hwconfig 'j9:disabled;j10:disabled;j11:pcie'; saveenv |
| 455 | | }}} |
| 456 | | |
| 457 | | '''Note that {{{hwconfig}}} is also used for serial configuration so care should be taken to preserve that configuration if used''' |
| 458 | | |
| 459 | | [=#serialconfig] |
| 460 | | ==== hwconfig: serial Configuration ==== |
| 461 | | Many boards in the Newport product family provide a 5-pin off-board serial connector that provides the following options: |
| 462 | | - 1x RS485 FD (UART2) |
| 463 | | - 1x RS485 HD (UART2) |
| 464 | | - 1x RS232 w/ hardware flow control (UART2) |
| 465 | | - 2x RS232 w/o hardware flow control (UART2/UART3) |
| 466 | | |
| 467 | | By default 2x RS232 with no flow control is enabled. To configure a different option use the {{{hwconfig}}} U-Boot env variable. The {{{mode}}} property of the {{{serial}}} option defines the initial configuration of the serial port(s). If RS485 is selected by the {{{mode}}} property the {{{term}}} property will select whether or not on-board termination is enabled. |
| 468 | | |
| 469 | | The {{{mode}}} property can have the following values: |
| 470 | | * rs232 - 2x RS232 (UART2/UART3) without hardware flow control (default if not specified) |
| 471 | | * rs232_dtr - RS232 (UART2) with hardware flow control |
| 472 | | * rs485_hd - RS485 half-duplex |
| 473 | | * rs485_fd - RS485 full-duplex |
| 474 | | |
| 475 | | Examples: |
| 476 | | * enable RS485 half duplex no on-board termination |
| 477 | | {{{#!bash |
| 478 | | setenv hwconfig "serial:mode=rs485_hd,term=no"; saveenv |
| 479 | | }}} |
| 480 | | * enable RS485 full duplex with on-board termination |
| 481 | | {{{#!bash |
| 482 | | setenv hwconfig "serial:mode=rs485_fd,term=yes"; saveenv |
| 483 | | }}} |
| 484 | | * enable RS232 with hardware flow-control: |
| 485 | | {{{#!bash |
| 486 | | setenv hwconfig "serial:mode=rs232_dtr"; saveenv |
| 487 | | }}} |
| 488 | | |
| 489 | | |
| 490 | | '''Note that {{{hwconfig}}} is also used for serial configuration so care should be taken to preserve that configuration if used''' |
