Changes between Initial Version and Version 1 of sbcrevisions


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Timestamp:
10/22/2017 05:28:45 AM (2 years ago)
Author:
trac
Comment:

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  • sbcrevisions

    v1 v1  
     1= Gateworks Single Board Computers Revisions =
     2[[PageOutline]]
     3
     4This page is to describe the difference between hardware revisions.
     5
     6= Ventana Family =
     7
     8== GW51xx ==
     9
     10== GW520x ==
     11=== Revision A ===
     12Date: 10/18/2013
     13
     14 * Initial Release
     15
     16=== Revision A.1 ===
     17Date: 10/18/2013
     18 * Replace decoupling capacitors on the clock buffer input with series resistors for improved PCIe clock performance.
     19
     20=== Revision B.1 ===
     21Date: 1/30/2014
     22 * Add !WiFi disable signal to all Mini-PCIe sockets through zero ohm resistors
     23 * Add optional load JST 1x2x2mm connector under the pushbutton switch
     24 * Add ability to route USB OTG to miniPCIe socket instead of front-panel via GPIO
     25 * Replace 2-pin tamper switch connector with 3-pin connector to support CAN Bus, RS485, TTL serial and tamper switch option
     26 * Add optional CAN Bus transceiver
     27 * Add optional RS485 transceiver
     28 * Add optional TTL serial bypass resistors
     29 * Add option for 3.3V and 5V power to one pin of the digital I/O connector through unloaded configuration resistors
     30
     31=== Revision C.1 ===
     32Date: 3/31/2015
     33 * Replace obsolete J2 uSD/SIM socket with functionally equivalent socket
     34 * Replace 3.3V TVS arrays with 2.5V arrays for improved protection
     35 * Add 3.3V voltage translator to both 2.5V PCISKTx_RSTJ signals for increased voltage margin
     36 * Remove capacitor on tamper switch input to reduce switch debounce time constant
     37 * Add Schottky diode to USB_H1_VBUS net to prevent i.MX6 backfeed when board is powered off and active USB cable is plugged in
     38 * Connect I2C3 bus to the digital I/O connector through unloaded configuration resistors
     39 * Connect GPS PPS signal to reserved pin on both Mini-PCIe sockets through unloaded configuration resistors
     40 * Add changes to support SOM application, (a) add CAN bus transceiver bypass resistors, (b) add RS232 transceiver bypass resistors, (c) add connector under uSD/SIM socket to support SD, USB, battery voltage, and reset, (d) add 2-pin power input connector
     41 * Add "USB" to PCIe socket silkscreen for clarification
     42
     43=== Revision C.2  ===
     44Date: 4/3/2015
     45 * Add 100 ohm differential PCIe clock termination resistor for improved PCIe clock compliance.
     46
     47=== Revision D  ===
     48Date: 2/18/2016
     49 * Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
     50 * Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
     51 * Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J11.5 as an option
     52 * Add optional GSC analog input to J4.1 connector through divide by two configuration resistors unloading the series resistor for backwards compatibility
     53 * Add optional 4-pin friction latching connector for micro-B OTG connector
     54 * Add optional OTG ID pulldown resistor to configure OTG port for host operation when optional 4-pin connector is loaded
     55 * Reduce PORJ pullup resistor value for faster rise time
     56 * Add series resistor between battery positive and reverse current diode for UL two level protection
     57 * Add processor watchdog support by connecting WDOG_B to PMIC PWRON input
     58 * Add support for UHS-1 MMC cards to run at their full speed capability
     59 * Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input
     60 * Replace RGMII_TXCLK series resistor with 22.1 ohm device and add second 22.1 series resistor to RGMII_RXCLK to reduce radiated emissions
     61 * Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
     62 * Update SIM/uSD socket footprint and move 0.2mm closer to board edge for improved manufacturing
     63 * Move USB signals away from SIM/uSD mounting tab slot to improve fabrication processes
     64
     65
     66
     67== GW53xx ==
     68=== Revision F ===
     69 * Improve 5V Boost Supply for powering CAN, HDMI, and LVDS. (see Resolves [wiki:ventana/errata#HW18GW53xx-CDE5Vinrushcurrentlimitedat100mA Errata HW18]
     70 * Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
     71 * Improve voltage rails with larger traces and capacitors for greater stability when operating in LDO-Bypass mode
     72 * Improve USB host connector durability
     73
     74== GW54xx ==
     75
     76=== Revision E ===
     77Date: 6/28/2016:
     78 * Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see [wiki:ventana/errata#hw8 Errata HW8])
     79 * Connect GPS PPS signal to reserved pin 49 of J9 (Top right) and J10 (Bottomr left/center) Mini-PCIe sockets through unloaded configuration resistors as a build option
     80 * Add 3.3V voltage translator to miniPCIe socket PERST# signals for increased voltage margin
     81 * Unload capacitor C473 to resolve issue with off-board tamper signal (see  [wiki:ventana/errata#hw4 Errata HW4])
     82 * Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
     83 * Add ability to bypass CAN transceiver through loadable resistors
     84 * Add ability to bypass UART2 RS232 transceiver through loadable resistors
     85 * Improved GPS Antenna short circuit fault monitoring by lowering trip threshold to allow for higher power active antennas
     86 * Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J28.5 as an option
     87 * Add 0 to 5V GSC analog input available via 3-byte register at 0x1A to previously unused J27.4 connector
     88 * Add resistor loading option to provide 3.3V to J16.3
     89 * Add resistor loading option to provide 5.0V to J16.4
     90 * Add series resistor between battery positive and reverse current diode for UL two level protection
     91 * Add processor watchdog support by connecting WDOG2_B to PMIC PWRON input (see [wiki:ventana/errata#hw12 Errata HW12])
     92 * Reduce PCIe clock jitter to GEN2 levels by routing clock generator output back to processor PCIe clock input (see [wiki:ventana/errata#hw14 Errata HW14])
     93 * Add support for UHS-1 MMC cards to run at their full speed capability (see [wiki:ventana/errata#hw16 Errata HW16])
     94 * Add a reset generator to improve signalling during board reset
     95 * Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills for greater stability when operating in LDO-Bypass mode as well as supporting higher frequency processors
     96 * Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
     97 * Improve USB host connector durability
     98 * Add SPI support via J32
     99
     100== GW551x ==
     101
     102== GW552x ==
     103
     104= Laguna Family =
     105
     106Please contact support
     107
     108= Other SBC Families =
     109
     110Please contact support