Changes between Version 3 and Version 4 of venice/errata

03/25/2022 10:43:04 PM (5 months ago)
Tim Harvey

added GPY111 PHY errata


  • venice/errata

    v3 v4  
     58== VN4 GPY111 PHY replacement
     60 * Due to supply chain limitations the DP83867 GbE PHY has been replaced with the GPY111 GbE PHY
     63 * Software support which is already present in the latest Venice Gateworks boot firmware is needed to support this PHY. If using older boot firmware the following patches are needed:
     64  - [ imx8mmm-venice-gw700x: add support for GPY111 phy] (for GW700x)
     65  - [ imx8m{m,n}-venice-gw7902: add support for GPY111 phy] (for GW7902)
     66  - [ net: fec: prevent undesired de-assertion of phy-reset on request]
     67  - [ board: gateworks venice: add support for GPY111 phy]
     69Affected Products:
     70 - GW700x-E+ (PCB 02210210-04) (SoM used on GW710x/GW720x/GW730x boards)
     71 - GW7902-C+ (PCB 02210224-02)
     74 - To determine what version of SoM your GW710x/GW720x/GW730x board uses use the 'gsc' command in U-Boot:
     76u-boot=> gsc
     77Model   : GW7300-00-B1B
     78Serial  : 852418
     79MFGDate : 10-20-2020
     80SOM     : GW7000-B 852418 10-20-2020
     81BASE    : GW7300-B1 849162 10-06-2020
     84 - If your software has the required support the PHY will be shown in U-Boot as follows:
     86Net:   GPY111 eth0: ethernet@30be0000 [PRIME]
     91== VN5 GPY111 PHY bit error rate and link errata
     94 * The GPY111 PHY used on a variety of boards in the Venice product family has some errata from the manufacturer that affects Venice products:
     95  1. When operating on a GbE link occasionally a link will have a high CRC error rate directly after a cable plug-in or board power-up event. A link down/up event will typically resolve this issue.
     98 - Issue #1 is addressed internally by firmware in the PHY: If the PHY exceeds an allowed threshold of 'Start-of-Stream Delimiter' (SSD) errors it will restart link negotiation a number of times before finally giving up and will then 'Auto-Downspeed' (ADS) to a 100mbps link. This feature is configured by the PHY LSADS field (bit 15 - 14) of the PHY_PHYCTL2 MII register (0x14) where a value of 00b is Off (ADS disabled), 01B will retry 1 time, 10B will retry 3 times (default), and 11B will retry 4 times. An ADS event is signaled by the LSADS bit (bit 8) of the PHY_PHYSTAT1 (0x11) MII register being set. The overall affect of using ADS is that the link may not be stable until it has settled after the link is brought up and in rare cases the link may settle at 100mbps. In extensive testing it has been found that link retries occurs about 1 in 100 plug-in/power-up events, an Auto-Downspeed to 100m occurs less than 1 in 5000 plug-in/power-up events, and that the link is stable within 30 seconds.
     100Affected Products:
     101 - GW700x-E+ (PCB 02210210-04)
     102 - GW7902-C+
     103 - GW7903-A+