Changes between Version 2 and Version 3 of venice/ethernet


Ignore:
Timestamp:
08/08/2022 09:46:29 PM (4 months ago)
Author:
Tim Harvey
Comment:

updated notes

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  • venice/ethernet

    v2 v3  
    2121|| GW710x  || J16  || Ethernet || eth0 || eth0 || IMX8MM FEC RGMII GPY111 || Passive 8-60V PoE ||
    2222 * Port ordering above is from leftmost RJ45 on board when viewing the front-panel
     23 * if 'net.ifnames=0' kernel parameter is specified network interfaces on enumerated busses such as pci/usb are numbered sequentially (ie eth1 instead of enp6s0). See [https://systemd.io/PREDICTABLE_INTERFACE_NAMES/ Predictable Interface Names] for details
     24 * for boards like the GW740x which have a multi-port GbE switch, bandwidth is shared across the downstream ports
    2325