Changes between Version 112 and Version 113 of gsc

Timestamp:

12/19/2023 06:04:12 PM (5 months ago)

Author:

Ryan Erbstoesser

Comment:

update register 0 example

gsc

@@ -96 +96 @@
 || 6     || SWITCH_HOLD         || 0 = Switch hold disabled.[[BR]] 1 = Switch Hold On. When the switch is held down for >700ms an interrupt[[BR]] will be generated. See interrupt Enable / Status registers. (supported in rev29+) ||Disabled||Disabled||
 || 7     || CPU_WDOG_POWERCYCLE || 0 = Disabled. CPU WDOG signals only trigger a software reset. [[BR]] 1 = Enabled. Convert CPU WDOG signal into a full board power cycle. (GSCv3 only) || Enabled || Not supported ||
+
+Example: (does not represent defaults or any specific data)
+Read register 0:
+{{{
+i2cget -f -y 0 0x20 0
+0x89 #result
+}}}
+
+10001001 is the binary form for 0x89
+
+Bit 0 is 'set' and is the LSB (least significant bit) on the far 'right' of the binary sequence.
+Bit 7 is 'set' and the MSB on the far 'left' of the binary sequence.
+
+Thus, the example to clear bit 7 would be to change the 0x89 to 0x09
+{{{
+i2cset -f -y 0 0x20 0 0x09
+}}}
 
 [=#gsc_ctrl_1]