Changes between Version 28 and Version 29 of gsc


Ignore:
Timestamp:
12/07/2018 11:24:38 PM (5 years ago)
Author:
Tim Harvey
Comment:

added GSC v53 details

Legend:

Unmodified
Added
Removed
Modified

  • gsc

    v28 v29  
    631631||          || GW2391  || Yes                      || Yes        ||
    632632
     633
     634
     635[=#reset-cause]
     636== GSC Reset Cause (GSCv3)
     637On most boards, the Gateworks System Controller has the ability to disable primary board power. This is used as a form of 'hard reset' in many cases. You can determine if and why the board was hard reset by looking at the value of the GSC_RESET_CAUSE register.
     638
     639Note that the Newport boot firmware will display the reason on bootup. Note that the value of 0, reported as 'VIN' indicates the GSC did not reset the board power supply and the board powered up because of Vin being applied externally.
     640
     641
     642[=#thermal-protection]
     643== GSC Thermal Protection (GSCv3)
     644The Gateworks System Controller has the ability to monitor board temperature and CPU temperature and disable board primary power when either of those exceeds specified values.
     645
     646If either the GSC 'board temperature' exceeds 85C or the 'external thermal sensor' exceeds its threshold (100C for Newport CPU Junction Temperature (Tj)) the GSC will disable the primary power supply for a 'cooldown period'. The cooldown period has a minimum of 5 seconds, a maximum of 300 seconds, and will increase by 30 seconds each time a thermal threshold event occurs. If no thermal threshold event occurs within 300 seconds of power-up the cooldown period will be reset to the minimum of 5 seconds.
     647
     648This feature is present on:
     649 - GW6100-A+
     650 - GW6200-A+
     651 - GW6300-D+
     652 - GW6400-B+
     653
     654This can be enabled with the GSC_THERMAL_PROTECT register R19 by setting bit 0.
     655
     656Examples:
     657 * U-Boot:
     658{{{#!bash
     659# Enable thermal protection
     660i2c dev 0 && i2c mw 0x20 0x13 1
     661# Disable thermal protection
     662i2c dev 0 && i2c mw 0x20 0x13 0
     663}}}
     664 * Linux:
     665{{{#!bash
     666# Enable thermal protection
     667i2cset -f -y 0 0x20 19 1
     668# Disable thermal protection
     669i2cset -f -y 0 0x20 19 0
     670}}}
     671
     672
    633673[=#gsc-interrupts]
    634 == GSC Interrupts ==
     674== GSC Interrupts
    635675The Gateworks System Controller has an interrupt signal to the host processor which it asserts when an event has occurred worth notifying the host about. The GSC_INTERRUPT_ENABLE register defines what events can trigger an interrupt and an interrupt service routine can query the GSC_INTERRUPT_STATUS register to see what events are present. The interrupt remains asserted until all status bits are cleared by writing 0's to those bits in the GSC_INTERRUPT_STATUS register.
    636676
    … …  
    783823 * see [wiki:watchdog] for more info on watchdogs in general
    784824
     825
    785826[=#registers]
    786 == GSC Registers ==
     827== GSC Registers
    787828The System Specialized Functions described above are configured via a set of GSC registers in an i2c slave device at the 7-bit address of 0x20.
    788829
    789830GSC Registers:
    790 ||= Reg Number =||= Reg Name           =||= Description                                 =||
    791 || 0            || GSC_CTRL_0           || Pushbutton Switch, CRC, Tamper Switch         ||
    792 || 1            || GSC_CTRL_1           || Sleep / Wakeup Control, Alternate Boot Device ||
    793 || 2-5          || GSC_SLEEP_WAKE_TIME  || Sleep Wakeup Timer                            ||
    794 || 6-9          || GSC_SLEEP_ADD        || Sleep Wakeup Additive Timer                   ||
    795 || 10           || GSC_INTERRUPT_SOURCE || Interrupt Source                              ||
    796 || 11           || GSC_INTERRUPT_ENABLE || Interrupt Enable                              ||
    797 || 12-13        || GSC_FIRMWARE_CRC     || Firmware CRC Value                            ||
    798 || 14           || GSC_FIRMWARE_VER     || Firmware Version                              ||
    799 || 15           || GSC_WRITE_PROTECT    || Write Protection                              ||
     831||= Reg Number =||= Reg Name           =||= Description                                 =||= Supported =||
     832|| 0            || GSC_CTRL_0           || Pushbutton Switch, CRC, Tamper Switch         || All ||
     833|| 1            || GSC_CTRL_1           || Sleep / Wakeup Control, Alternate Boot Device || All ||
     834|| 2-5          || GSC_SLEEP_WAKE_TIME  || Sleep Wakeup Timer                            || All ||
     835|| 6-9          || GSC_SLEEP_ADD        || Sleep Wakeup Additive Timer                   || All ||
     836|| 10           || GSC_INTERRUPT_SOURCE || Interrupt Source                              || All ||
     837|| 11           || GSC_INTERRUPT_ENABLE || Interrupt Enable                              || All ||
     838|| 12-13        || GSC_FIRMWARE_CRC     || Firmware CRC Value                            || All ||
     839|| 14           || GSC_FIRMWARE_VER     || Firmware Version                              || All ||
     840|| 15           || GSC_WRITE_PROTECT    || Write Protection                              || All ||
     841|| 16           || GSC_RESET_CAUSE      || Reset Cause                                   || GSCv3 ||
     842|| 19           || GSC_THERMAL_PROTECT  || Thermal Protection                            || GSCv3 ||
     843
    800844
    801845[=#gsc_ctrl_0]
    802 === GSC_CTRL_0 (Register R0): Pushbutton Switch, CRC, and Tamper Switch configuration ===
     846=== GSC_CTRL_0 (Register R0): Pushbutton Switch, CRC, and Tamper Switch configuration
    803847||= Bit =||= Name              =||= Description =||=Newport Defaults=||=Ventana Defaults||
    804848|| 0     || PB_HARD_RESET       || 0 = Pushbutton Software Interrupt[[BR]] Generates GSC Interrupt (see R10.0/R11.0)[[BR]] 1 = Push button generates hard system reset to board when the button is[[BR]] activated and de-activated within 700ms ||Enabled||Enabled||
    … …  
    812856
    813857[=#gsc_ctrl_1]
    814 === GSC_CTRL_1 (Register R1): Sleep Wakeup Timer Control ===
     858=== GSC_CTRL_1 (Register R1): Sleep Wakeup Timer Control
    815859||= Bit =||= Name              =||= Description =||
    816860|| 0     || SLEEP_ENABLE        || 0 = Disable hardware sleep operation[[BR]] 1 = Enable hardware sleep operation ||
    … …  
    824868
    825869[=#gsc_sleep_wake_time]
    826 === GSC_SLEEP_WAKE_TIME (Registers R2-R5): Sleep Wakeup Time ===
     870=== GSC_SLEEP_WAKE_TIME (Registers R2-R5): Sleep Wakeup Time
    827871||= Bit =||= Description =||
    828872|| 0-31  || RTC Value to wake the board when in sleep[[BR]] (least significant byte first) ||
    829873
    830874[=#gsc_sleep_add]
    831 === GSC_SLEEP_ADD (Registers R6-R9): Sleep Wakeup Time Additive ===
     875=== GSC_SLEEP_ADD (Registers R6-R9): Sleep Wakeup Time Additive
    832876||= Bit =||= Description =||
    833877|| 0-31  || Add to current RTC and store in GSC_SLEEP_WAKE_TIME[[BR]] latched with R1.2[[BR]] (least significant byte first) ||
    834878
    835879[=#gsc_interrupt_status]
    836 === GSC_INTERRUPT_STATUS (Register R10): Interrupt Source ===
     880=== GSC_INTERRUPT_STATUS (Register R10): Interrupt Source
    837881The GSC includes a single active-low level-triggered interrupt connected to an interrupt input on the ARM host processor. The GSC includes several possible interrupt sources with a control register to enable the desired interrupts and a status register to determine which are active. The following bits will indicate the cause of the host interrupt assertion which will remain asserted until all enabled bits are clear.
    838882
    … …  
    850894
    851895[=#gsc_interrupt_enable]
    852 === GSC_INTERRUPT_ENABLE (Register R11): Interrupt Enable (refer to bits above) ===
     896=== GSC_INTERRUPT_ENABLE (Register R11): Interrupt Enable (refer to bits above)
    853897||= Bit =||= Name =||= Description =||
    854898|| 0     || IRQ_PB                || Set to enable pushbutton switch interrupt ||
    … …  
    864908
    865909[=#gsc_firmware_crc]
    866 === GSC_FIRMWARE_CRC (Register R12,R13): GSC Firmware CRC Value ===
     910=== GSC_FIRMWARE_CRC (Register R12,R13): GSC Firmware CRC Value
    867911||= Bit  =||= Description =||
    868912||  0-15  || Contains the 16-bit cyclic redundancy check value for the GSP Flash memory (least significant byte first)[[BR]] The GSC performs a CRC check when R0.4 is set[[BR]] Once R0.4 is clear, R12 and R13 (16-bit lsb) contain an accurate CRC. ||
    … …  
    870914
    871915[=#gsc_firmware_ver]
    872 === GSC_FIRMWARE_VER (Register R14): GSC Firmware Version ===
     916=== GSC_FIRMWARE_VER (Register R14): GSC Firmware Version
    873917||= Bit =||= Description                            =||
    874918|| 0-7   || Contains the GSC firmware version number ||
    … …  
    876920
    877921[=#gsc_write_protect]
    878 === GSC_WRITE_PROTECT (Register R15): Write Protection ===
     922=== GSC_WRITE_PROTECT (Register R15): Write Protection
    879923||= Bit =||= Name =||= Description                                                                                      =||
    880924|| 0     || GSC_EEPROM_WP_ALL       || 1 = Write Protect all EEPROM regions                                              ||
    … …  
    883927|| 3-7   || GSC_WP_PASSWD           || Must be 0xB when altering bits[0:2] (ie write 0x59 (0xB<<3|0x1) to enable WP_ALL) ||
    884928
    885 == Code Examples ==
     929[=#gsc_reset_cause]
     930=== GSC_RESET_CAUSE (Register R16): Reset Cause
     931Supported on GSCv3, the GSC_RESET_CAUSE register describes the event that caused the boards power supply to be reset by the GSC.
     932
     933||= Value =||= Name =||= Description =||
     934|| 0  || RST_CAUSE_VIN             || Board power was applied - normal powerup; no reset ||
     935|| 1  || RST_CAUSE_PB              || User pushbutton ||
     936|| 2  || reserved                  || reserved ||
     937|| 3  || RST_CAUSE_CPU             || CPU watchdog ||
     938|| 4  || RST_CAUSE_TEMP_LOCAL      || Board Temperature exceeded spec ||
     939|| 5  || RST_CAUSE_TEMP_REMOTE     || CPU Temperature exceeded spec ||
     940|| 6  || RST_CAUSE_SLEEP           || GSC woke board from sleep ||
     941|| 7  || RST_CAUSE_BOOT_WDT        || Boot watchdog ||
     942|| 8  || RST_CAUSE_BOOT_WDT_MANUAL || User pushbutton 5x to toggle boot device ||
     943|| 9  || RST_CAUSE_SOFT_PWR        || Button press from soft power control ||
     944
     945[=#gsc_thermal_protect]
     946=== GSC_THERMAL_PROTECT (Register R19): Thermal Protection Configuration
     947Supportedon GSCv3, the GSC_THERMAL_PROTECT register configures the thermal protection feature.
     948
     949||= Bit =||= Name =||= Description                                                                                      =||
     950|| 0     || GSC_TP_ENABLE || 1 = Enable Thermal protection ||                                     
     951
     952
     953== Code Examples
    886954
    887955The following examples show how to utilize some of the GSC features and functions.
    … …  
    12071275
    12081276The following represents the revision history for externally released GSC firmware revisions:
     1277- GSCv3 (Newport):
     1278 * v53: 20181107
     1279  - fix pushbutton soft power down
     1280  - fix restart behavior after JTAG programming
     1281  - fix ADC precision
     1282  - add ability to disable full board power cycle on CPU reset
     1283  - add reset cause register
     1284  - add thermal protection
    12091285 * v52: 20180518
    1210   - GW630x:
    1211     - add fan tach support
    1212     - add power glitch protection
    1213     - fix various power draw issues
    1214     - fix PCA9555 emulation (pushbutton, tamper, WLAN disable)
    1215       - improved the latency on GPIO_CHANGE events (from 1s max to 10ms max)
    1216       - Note that this changed the Newport user pb gpio from P0.0 to P0.2 (device-tree change)
    1217     - fixed VDD_VBATT calculation
     1286  - add fan tach support
     1287  - add power glitch protection
     1288  - fix various power draw issues
     1289  - fix PCA9555 emulation (pushbutton, tamper, WLAN disable)
     1290    - improved the latency on GPIO_CHANGE events (from 1s max to 10ms max)
     1291    - Note that this changed the Newport user pb gpio from P0.0 to P0.2 (device-tree change)
     1292  - fixed VDD_VBATT calculation
    12181293 * v51: 20180405
    1219   - GW630x:
    1220     - fix various power draw issues
    1221     - fix issue with MCU_IRQ
    1222     - convert to raw ADC's (ADCs now continually update instead of only at 1Hz)
    1223     - add gsc-update support
    1224     - fix issues causing occasional NAK's
     1294  - fix various power draw issues
     1295  - fix issue with MCU_IRQ
     1296  - convert to raw ADC's (ADCs now continually update instead of only at 1Hz)
     1297  - add gsc-update support
     1298  - fix issues causing occasional NAK's
     1299- GSCv1 / GSCv2 (Ventana / Laguna):
    12251300 * v50:
    12261301  - address an issue which could cause unexpected power draw from GSC battery from
    … …  
    12631338Latest GSC revisions per baseboard:
    12641339||= family =||= board =||= revision =||
    1265 || Newport  || GW640x  || [http://dev.gateworks.com/newport/images/gsc_640x_v52-20180518-g2438118-bf2d.txt v52] ||
    1266 ||          || GW630x  || [http://dev.gateworks.com/newport/images/gsc_630x_v52-20180518-g2438118-bf2d.txt v52] ||
     1340|| Newport  || GW640x  || [http://dev.gateworks.com/newport/images/gsc_640x.txt v53] ||
     1341||          || GW630x  || [http://dev.gateworks.com/newport/images/gsc_630x.txt v53] ||
     1342||          || GW620x  || [http://dev.gateworks.com/newport/images/gsc_620x.txt v53] ||
     1343||          || GW610x  || [http://dev.gateworks.com/newport/images/gsc_610x.txt v53] ||
    12671344||||
    12681345|| Ventana  || GW553x  || [http://dev.gateworks.com/ventana/images/gsc_553x_v50.txt v50] ||
    … …  
    12941371The shelf life of the battery defines how long the GSC retains power and thus its settings such as the RTC when board power is removed and depends on the version of the GSC:
    12951372 * GSCv3 (Newport): approximately 5.7 years
    1296  * GSCv1/GSCv2 (Ventana/Laguna): approximately 3.8 years
     1373 * GSCv1/GSCv2 (Ventana / Laguna): approximately 3.8 years
    12971374
    12981375