Changes between Version 57 and Version 58 of gsc


Ignore:
Timestamp:
07/29/2020 04:33:36 PM (4 years ago)
Author:
Tim Harvey
Comment:

remove obsolete user watchdog feature info

Legend:

Unmodified
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  • gsc

    v57 v58  
    1313 * [wiki:gsc#TamperDetection Tamper detection]
    1414 * [wiki:gsc#GPSActiveAntennashort-circuitauto-detectandrecover GPS Active Antenna short-circuit auto-detect and recover]
    15  * [wiki:gsc#HardwareWatchdog Hardware Watchdog]
     15 * [wiki:gsc#HardwareWatchdog Hardware Boot Watchdog]
    1616 * [wiki:gsc#resetmonitor Reset Monitor]
    1717 * [wiki:gsc#GSCUpdates Software field-upgradable firmware]
    … …  
    660660
    661661=== Auto Switch Boot Device ===
    662 If the board is equipped with an ''Alternate Boot Device'' you can enable the GSC's ''Auto Switch Boot'' feature by setting R1.6 (SWITCH_BOOT_ENABLE). When a board powers on with this bit set, the watchdog timer will be set for a 30 second timeout when the board is powered on. If this timer expires the GSC will toggle the boot device and power-cycle the board. You can disable the timer for the current boot by setting R1.7 (SWITCH_BOOT_CLEAR) (it will be re-armed on the next power cycle in SWITCH_BOOT_ENABLE has not been cleared).
     662If the board is equipped with an ''Alternate Boot Device'' you can enable the GSC's ''Auto Switch Boot'' feature by setting R1.6 (SWITCH_BOOT_ENABLE). When a board powers on with this bit set if the 30 second boot watchdog timer expires the GSC will toggle the boot device and power-cycle the board. You can disable the timer for the current boot by setting R1.7 (SWITCH_BOOT_CLEAR) (it will be re-armed on the next power cycle in SWITCH_BOOT_ENABLE has not been cleared).
    663663
    664664For example, if you a supporting firmware updates in your product but want a mechanism to ensure a power loss or other event during a firmware update does not render your device recoverable you can enable this feature and put a 'recovery image' on the alternate boot device.  In this example both firmware images (the primary and the alternate) should set R1.7 within 30 seconds of bootup if that firmware image is desirable.  If either image fails to set R1.7 within the 30 seconds, the board will automatically boot to the other device.
    … …  
    814814[=#IRQ_WDOG_TIMEOUT]
    815815=== IRQ_WDOG_TIMEOUT interrupt ===
    816 The IRQ_WDOG_TIMEOUT interrupt indicates that the GSC watchdog caused a board level power cycle and as such can't be caught via software (as the board was power cycled) but can be detected at power-on as the reason for reset.
     816The IRQ_WDOG_TIMEOUT interrupt indicates that the GSC boot watchdog caused a board level power cycle and as such can't be caught via software (as the board was power cycled) but can be detected at power-on as the reason for reset.
    817817
    818818Note that the Ventana bootloader reads and clears this status register but displays the result.
    819819
    820 See also:
    821  * [#watchdog Hardware Watchdog]
    822820
    823821[=#watchdog]
    824 == Hardware Watchdog ==
    825 Ventana and Laguna boards with GSC v2 can benefit from a GSC Watchdog (requires v44 or later of GSC firmware). Note that Newport boards with a GSC v3 do not benefit from a GSC Watchdog as the external reset on the CN80XX/CN81XX is asserted when the CPU watchdog expires and is monitored by the GSC. The GSC on these boards will cause a primary board power supply reset when this occurs.
    826 
    827 A watchdog is a common feature which allows a timer to be configured such that a reset occurs if that timer expires. A software component will typically enable the watchdog timer and restart it periodically before the timer expires based on some conditions. Usually there is no specific condition so the timer gets restarted (avoiding a system reset) unless the CPU running that software hangs.
    828 
    829 Systems that want to place more criteria on the condition of restarting the watchdog can do so, such as checking various statistics or states. For example, you may wish to reset the board if the network connection ever goes away.
    830 
    831 Most modern CPU's have built-in watchdog elements, which will reset the CPU and sometimes drive an external signal which can reset various components on the board. For example, our Laguna products with NOR flash will reset the NOR flash when a watchdog reset occurs because we have found that without doing so the processor can hang on a CPU reset. The linux kernel supports CPU watchdogs with a driver and a well known userspace API, but in this scenario the watchdog is not enabled (and thus not protecting against hangs etc) until userspace init is reached.
    832 
    833 Sometimes, however, a CPU watchdog isn't adequate because there may be an issue which you are trying to protect against such as a hang before the watchdog is even enabled or perhaps an issue where a peripheral isn't reset on a watchdog event (because the hardware doesn't have a reset pin for example, or the board design did not connect it).
    834 
    835 Because the Gateworks System Controller has the ability to disable a board's primary power supply its the perfect place to implement a hardware watchdog. When the GSC's watchdog trips, it will power cycle the board vs a 'reset'. Furthermore, because the GSC watchdog re-arms on power-up when enabled you can protect against hangs over the full power-up of the board: primary program loader (ie CPU boot ROM), secondary program loader (oe uboot), kernel (ie Linux kernel), and userspace.
    836 
    837 Example usage:
    838  * Enable watchdog (with '''latest Ventana u-boot'''):
    839 {{{
    840 #!bash
    841 gsc wd enable 30 # enable watchdog for 30s timeout
    842 gsc wd enable 60 # enable watchdog for 60s timeout
    843 }}}
    844  * Enable watchdog (from older Ventana u-boot)
    845 {{{
    846 #!bash
    847 i2c dev 0 # GSC is on the first of several i2c busses
    848 i2c mw 0x20 1 0x20 1 # set R1=0x20 to enable watchdog for 30s timeout
    849 }}}
    850  * Enable watchdog (from Laguna u-boot)
    851 {{{
    852 #!bash
    853 imw 0x20 1 0x20 1 # set R1=0x20 to enable watchdog for 30s timeout
    854 imw 0x20 1 0x30 1 # set R1=0x30 to enable watchdog for 60s timeout
    855 }}}
    856  * Enable watchdog (from Linux)
    857 {{{
    858 #!bash
    859 i2cset -f -y 0 0x20 1 0x20 # set R1=0x20 to enable watchdog for 30s timeout
    860 i2cset -f -y 0 0x20 1 0x30 # set R1=0x30 to enable watchdog for 60s timeout
    861 }}}
    862  * Disable watchdog (from '''latest Ventana u-boot''')
    863 {{{
    864 #!bash
    865 gsc wd disable
    866 }}}
    867  * Disable watchdog (from older Ventana u-boot)
    868 {{{
    869 #!bash
    870 i2c dev 0 # GSC is on the first of several i2c busses
    871 i2c mw 0x20 1 0 1 # disable watchdog
    872 }}}
    873  * disable watchdog (from Laguna u-boot-2008)
    874 {{{
    875 #!bash
    876 imw 0x20 1 0 1 # disable watchdog
    877 }}}
    878  * disable watchdog (from Linux)
    879 {{{
    880 #!bash
    881 i2cset -f -y 0 0x20 1 0x00 # clear R1 to disable watchdog
    882 }}}
    883 
    884 In the above examples, notice that you are overwriting other bits that you may care about in R1 such as sleep enable. If you want a more foolproof way of adjusting just the bit you care about mask out the bits you want to set then OR in the value you want to set them to. For example, if you wish to set R1.4=0 and R1.5=1 you could to the following in shell:
    885 {{{
    886 #!bash
    887 R1=$(i2cget -f -y 0 0x20 1) && \
    888   R1=$((R1 & ~0x30)) && \
    889   R1=$((R1 |  0x20)) && \
    890   i2cset -f -y 0 0x20 1 $R1 || echo i2c error
    891 }}}
    892 
    893 Notes:
    894  * Once enabled, the GSC watchdog will re-arm on a power-up event (so that the board is protected from power-up onward). Because of this feature, if you have enabled the GSC watchdog:
    895   * if you break out of the bootloader you will need to disable the watchdog manually (see above)
    896   * if you use jtag_usb to program firmware you will need to be sure to use the most recent version which knows to disable the GSC watchdog
    897  * The Ventana GSC always uses the watchdog on power-up to cover some IMX6 errata which can cause the board to fail to boot from NAND. The bootloader disables the watchdog unless you have enabled it manually.
    898  * If you encounter difficulties once you have enabled the watchdog (ie your software is not resetting or disabling the watchdog, or your can't program the board via uboot or jtag) you can simply remove the GSC battery for 10seconds to reset the GSC to the default state where the watchdog is not enabled (this will of course reset all other registers you may have changed including the RTC).
    899  * see [wiki:gsc#GSCWatchdogkerneldriver below] for details on using the GSC watchdog via the Linux kernel driver and making sure you have a userspace application that tickles it
    900  * see [wiki:watchdog] for more info on watchdogs in general
     822== Hardware Boot Watchdog ==
     823Gateworks boards benefit from a GSC Boot Watchdog which will cause a primary board power supply reset if the bootloader fails to load and disable it within 30 seconds. This protects against occasional chip errata that our hardware has no control over.
    901824
    902825
    … …  
    945868|| 2     || LATCH_SLEEP_ADD     || 0 = Reserved[[BR]] 1 = Latch and add GSC_SLEEP_ADD registers to GSC_SLEEP_WAKE[[BR]]Resets to Zero on Completion ||
    946869|| 3     || SLEEP_NOWAKEPB      || 0 = Wake from sleep on pushbutton 1 = do not wake on sleep until sleep wakeup time ||
    947 || 4     || WATCHDOG_TIME       || 0 = 30 second timeout[[BR]] 1 = 60 second timeout ||
    948 || 5     || WATCHDOG_ENABLE     || 0 = disable watchdog[[BR]] 1 = Enable / Reset watchdog timer ||
     870|| 4     || RESERVED            || ||
     871|| 5     || RESERVED            || ||
    949872|| 6     || SWITCH_BOOT_ENABLE  || 0 = Auto Switch boot disabled[[BR]] 1 = Auto Switch boot enabled[[BR]]Note this is set and used at powerup by the GSC as a '''boot watchdog''' on Ventana boards ||
    950873|| 7     || SWITCH_BOOT_CLEAR   || Auto Switch boot clear[[BR]]Set to disable auto switch boot countdown timer[[BR]]Note this is set and used at bootup by the bootloader as a '''boot watchdog''' on Ventana boards ||
    … …  
    971894|| 4     || IRQ_GPIO_CHANGE   || When set a GPIO interrupt has occurred ||
    972895|| 5     || IRQ_TAMPER_DETECT || When set a tamper switch interrupt has occurred ||
    973 || 6     || IRQ_WDOG_TIMEOUT  || When set a watchdog timeout has occurred resulting in the board being reset ||
     896|| 6     || IRQ_WDOG_TIMEOUT  || When set a boot watchdog timeout has occurred resulting in the board being reset ||
    974897|| 7     || IRQ_SWITCH_HOLD   || When set a 'switch hold' interrupt has occurred ||
    975898
    … …  
    985908|| 4     || IRQ_GPIO_CHANGE       || Set to enable GPIO interrupt ||
    986909|| 5     || IRQ_TAMPER_DETECT     || Set to enable Tamper detect interrupt ||
    987 || 6     || IRQ_WDOG_TIMEOUT      || Set to enable Watchdog timeout interrupt ||
     910|| 6     || IRQ_WDOG_TIMEOUT      || Set to enable Boot Watchdog timeout interrupt ||
    988911|| 7     || IRQ_SWITCH_HOLD       || Set to enable pushbutton switch 'hold' interrupt ||
    989912
    … …  
    14241347    hard reset enabled. This resolves some reset issues when using push-button reset on Ventana
    14251348 * v45 - bugfix: fix occasional GSC reset during flash EEPROM write
    1426  * v44 - added GSC hardware watchdog
     1349 * v44 - added GSC hardware boot watchdog
    14271350 * v43 - Ventana bugfix:
    14281351  - Fix Ventana [http://trac.gateworks.com/wiki/ventana/serial_downloader boot recovery mode]
    … …  
    14781401The following items are reset if the battery is removed for more than 10 seconds or if the GSC firmware has been updated:
    14791402 * RTC value (reset to 0 seconds since midnight Jan 1 1970)
    1480  * GSC configuration registers (R0's reset value varies from board to board, the others default to 0). Note that if using firmware v48 or later, you can program the 'firmware reset value' of R0 and R1 by writing to i2c eeprom slave 0x51 offset 0x50 and 0x51:
    1481 {{{
    1482 #!bash
    1483 # to set the default value of R0 to 0x04 (soft interrupt / soft power control)
    1484 i2c dev 0 && i2c mw 0x51 0x50 0x04 1 # write 0x04 to 0x51:0x50
    1485 # to set the default value of R1 to 0x30 to enable 60s watchdog
    1486 i2c dev 0 && i2c mw 0x51 0x51 0x30 1 # write 0x30 to 0x51:0x51
    1487 }}}
     1403 * GSC configuration registers (R0's reset value varies from board to board, the others default to 0).
    14881404 * Fan controller registers default to the temperature setpoints shown in the Fan Controller section above
    14891405 * '''Secure Key''' EEPROM area is set to 0xff's (see EEPROM section above)