Changes between Version 65 and Version 66 of gsc


Ignore:
Timestamp:
01/05/2021 01:08:54 AM (20 months ago)
Author:
Bobby Jones
Comment:

Shift gsc registers to top of page

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  • gsc

    v65 v66  
    5656  - reduced power consumption resulting in longer battery life (3.8Y -> 5Y)
    5757  - resolves 'high power draw state' when inserting a battery while board powered off
     58
     59
     60[=#registers]
     61== GSC Registers
     62The System Specialized Functions described above are configured via a set of GSC registers in an i2c slave device at the 7-bit address of {{{0x20}}}.
     63
     64GSC Registers:
     65||= Reg Number =||= Reg Name           =||= Description                                 =||= Supported =||
     66|| 0            || GSC_CTRL_0           || Pushbutton Switch, CRC, Tamper Switch         || All ||
     67|| 1            || GSC_CTRL_1           || Sleep / Wakeup Control, Alternate Boot Device || All ||
     68|| 2-5          || GSC_SLEEP_WAKE_TIME  || Sleep Wakeup Timer                            || All ||
     69|| 6-9          || GSC_SLEEP_ADD        || Sleep Wakeup Additive Timer                   || All ||
     70|| 10           || GSC_INTERRUPT_SOURCE || Interrupt Source                              || All ||
     71|| 11           || GSC_INTERRUPT_ENABLE || Interrupt Enable                              || All ||
     72|| 12-13        || GSC_FIRMWARE_CRC     || Firmware CRC Value                            || All ||
     73|| 14           || GSC_FIRMWARE_VER     || Firmware Version                              || All ||
     74|| 15           || GSC_WRITE_PROTECT    || Write Protection                              || All ||
     75|| 16           || GSC_RESET_CAUSE      || Reset Cause                                   || GSCv3 ||
     76|| 17           || GSC_INTERRUPT_SOURCE_1 || Interrupt Source 1                          || GSCv3 ||
     77|| 18           || GSC_INTERRUPT_ENABLE_1 || Interrupt Enable 1                          || GSCv3 ||
     78|| 19           || GSC_THERMAL_PROTECT  || Thermal Protection                            || GSCv3 ||
     79|| 20           || GSC_CPU_SPEED_CTRL   || CPU Speed Control                             || GSCv3 ||
     80|| 21           || GSC_BOOT_OPTIONS     || Boot Control Options                          || GSCv3 ||
     81|| 22           || GSC_MEM_ACCESS_PAGE  || Direct Memory Access Page Number              || GSCv3 ||
     82|| 23           || GSC_CTRL_2           || Pushbutton Switch, Misc.                      || GSCv3 ||
     83|| 31           || GSC_REGISTER_BACKUP  || Thermal Protection                            || GSCv3 ||
     84
     85[=#gsc_ctrl_0]
     86=== GSC_CTRL_0 (Register R0): Pushbutton Switch, CRC, and Tamper Switch configuration
     87||= Bit =||= Name              =||= Description =||=Newport Defaults=||=Ventana Defaults||
     88|| 0     || PB_HARD_RESET       || 0 = Pushbutton Software Interrupt[[BR]] Generates GSC Interrupt (see R10.0/R11.0)[[BR]] 1 = Push button generates hard system reset to board when the button is[[BR]] activated and de-activated within 700ms ||Enabled||Enabled||
     89|| 1     || PB_CLEAR_SECURE_KEY || 0 = Clear '''Secure Key''' EEPROM disabled[[BR]] 1 = Clear GSC EEPROM user space when switch is activated three times with[[BR]] less than 700ms delay between each activation[[BR]] Generates GSC Intterupt ||Disabled||Disabled||
     90|| 2     || PB_SOFT_POWER_DOWN  || 0 = Soft Power Down disabled[[BR]] 1 = Soft Power Down enabled[[BR]]Hold down >1s to power down[[BR]]When powered down a momentary press will power up[[BR]] Generates push button interrupt ||Disabled||Disabled||
     91|| 3     || PB_BOOT_ALTERNATE   || 0 = Boot Alternate Device disabled.[[BR]] 1 = Boot Alternate Device Enabled[[BR]] The board will reset and boot from the Alternate Boot Device when the[[BR]] pushbutton is activated (quick press-and-release) 5 times in quick succession) ||Enabled||Disabled||
     92|| 4     || PERFORM_CRC         || 1 = Run CRC on GSC and store results in GSC_FIRMWARE_CRC (R12,R13)[[BR]] resets to 0 on completion of CRC ||Disabled||Disabled||
     93|| 5     || TAMPER_DETECT       || 0 = Do not activate tamper switch operation[[BR]] 1 = Activate tamper switch operation. When Activated, if the tamper switch[[BR]] is released, the contents in the EEPROM user space will be erased[[BR]] Generates tamper switch interrupt. ||Disabled||Disabled||
     94|| 6     || SWITCH_HOLD         || 0 = Switch hold disabled.[[BR]] 1 = Switch Hold On. When the switch is held down for >700ms an interrupt[[BR]] will be generated. See interrupt Enable / Status registers. (supported in rev29+) ||Disabled||Disabled||
     95|| 7     || CPU_WDOG_POWERCYCLE || 0 = Disabled. CPU WDOG signals only trigger a software reset. [[BR]] 1 = Enabled. Convert CPU WDOG signal into a full board power cycle. (GSCv3 only) || Enabled || Not supported ||
     96
     97[=#gsc_ctrl_1]
     98=== GSC_CTRL_1 (Register R1): Sleep Wakeup Timer Control
     99||= Bit =||= Name              =||= Description =||
     100|| 0     || SLEEP_ENABLE        || 0 = Disable hardware sleep operation[[BR]] 1 = Enable hardware sleep operation ||
     101|| 1     || ACTIVATE_SLEEP      || 0 = Do not activate hardware sleep operation[[BR]] 1 = Activate hardware sleep operation (see GSC_SLEEP_WAKE) ||
     102|| 2     || LATCH_SLEEP_ADD     || 0 = Reserved[[BR]] 1 = Latch and add GSC_SLEEP_ADD registers to GSC_SLEEP_WAKE[[BR]]Resets to Zero on Completion ||
     103|| 3     || SLEEP_NOWAKEPB      || 0 = Wake from sleep on pushbutton 1 = do not wake on sleep until sleep wakeup time ||
     104|| 4     || RESERVED            || ||
     105|| 5     || RESERVED            || ||
     106|| 6     || SWITCH_BOOT_ENABLE  || 0 = Auto Switch boot disabled[[BR]] 1 = Auto Switch boot enabled[[BR]]Note this is set and used at powerup by the GSC as a '''boot watchdog''' on Ventana boards ||
     107|| 7     || SWITCH_BOOT_CLEAR   || Auto Switch boot clear[[BR]]Set to disable auto switch boot countdown timer[[BR]]Note this is set and used at bootup by the bootloader as a '''boot watchdog''' on Ventana boards ||
     108
     109[=#gsc_sleep_wake_time]
     110=== GSC_SLEEP_WAKE_TIME (Registers R2-R5): Sleep Wakeup Time
     111||= Bit =||= Description =||
     112|| 0-31  || RTC Value to wake the board when in sleep[[BR]] (least significant byte first) ||
     113
     114[=#gsc_sleep_add]
     115=== GSC_SLEEP_ADD (Registers R6-R9): Sleep Wakeup Time Additive
     116||= Bit =||= Description =||
     117|| 0-31  || Add to current RTC and store in GSC_SLEEP_WAKE_TIME[[BR]] latched with R1.2[[BR]] (least significant byte first) ||
     118
     119[=#gsc_interrupt_status]
     120=== GSC_INTERRUPT_STATUS (Register R10): Interrupt Source
     121The GSC includes a single active-low level-triggered interrupt connected to an interrupt input on the ARM host processor. The GSC includes several possible interrupt sources with a control register to enable the desired interrupts and a status register to determine which are active. The following bits will indicate the cause of the host interrupt assertion which will remain asserted until all enabled bits are clear.
     122
     123||= Bit =||= Name =||= Description =||
     124|| 0     || IRQ_PB            || When set a pushbutton switch interrupt has occurred ||
     125|| 1     || IRQ_KEY_ERASED    || When set a '''Secure Key''' erase operation has completed ||
     126|| 2     || IRQ_EEPROM_WP     || When set an EEPROM WP violation occurred[[BR]] (write to EEPROM while GSC_EEPROM_WP_ALL or GSC_EEPROM_WP_BOARDINFO was enabled) ||
     127|| 3     ||                   || Reserved ||
     128|| 4     || IRQ_GPIO_CHANGE   || When set a GPIO interrupt has occurred ||
     129|| 5     || IRQ_TAMPER_DETECT || When set a tamper switch interrupt has occurred ||
     130|| 6     || IRQ_WDOG_TIMEOUT  || When set a boot watchdog timeout has occurred resulting in the board being reset ||
     131|| 7     || IRQ_SWITCH_HOLD   || When set a 'switch hold' interrupt has occurred ||
     132
     133For more information see [#gsc-interrupts gsc-interrupts]
     134
     135[=#gsc_interrupt_enable]
     136=== GSC_INTERRUPT_ENABLE (Register R11): Interrupt Enable (refer to bits above)
     137||= Bit =||= Name =||= Description =||
     138|| 0     || IRQ_PB                || Set to enable pushbutton switch interrupt ||
     139|| 1     || IRQ_SECURE_KEY_ERASED || Set to enable '''Secure Key''' erase operation interrupt ||
     140|| 2     || IRQ_EEPROM_WP         || Set to enable EEPROM WP violation interrupt ||
     141|| 3     ||                       || Reserved ||
     142|| 4     || IRQ_GPIO_CHANGE       || Set to enable GPIO interrupt ||
     143|| 5     || IRQ_TAMPER_DETECT     || Set to enable Tamper detect interrupt ||
     144|| 6     || IRQ_WDOG_TIMEOUT      || Set to enable Boot Watchdog timeout interrupt ||
     145|| 7     || IRQ_SWITCH_HOLD       || Set to enable pushbutton switch 'hold' interrupt ||
     146
     147For more information see [#gsc-interrupts gsc-interrupts]
     148
     149[=#gsc_firmware_crc]
     150=== GSC_FIRMWARE_CRC (Register R12,R13): GSC Firmware CRC Value
     151||= Bit  =||= Description =||
     152||  0-15  || Contains the 16-bit cyclic redundancy check value for the GSP Flash memory (least significant byte first)[[BR]] The GSC performs a CRC check when R0.4 is set[[BR]] Once R0.4 is clear, R12 and R13 (16-bit lsb) contain an accurate CRC. ||
     153
     154
     155[=#gsc_firmware_ver]
     156=== GSC_FIRMWARE_VER (Register R14): GSC Firmware Version
     157||= Bit =||= Description                            =||
     158|| 0-7   || Contains the GSC firmware version number ||
     159
     160
     161[=#gsc_write_protect]
     162=== GSC_WRITE_PROTECT (Register R15): Write Protection
     163||= Bit =||= Name =||= Description =||
     164|| 0     || GSC_EEPROM_WP_ALL || 1 = Write Protect all EEPROM regions ||
     165|| 1     || GSC_EEPROM_WP_BOARDINFO || 1 = Write Protect the reserved Gateworks '''Board Info''' EEPROM section          ||
     166|| 2     || Reserved || - ||
     167|| 3-7   || GSC_WP_PASSWD || Must be 0xB when altering bits[0:2] (ie write 0x59 (0xB<<3|0x1) to enable WP_ALL) ||
     168
     169[=#gsc_reset_cause]
     170=== GSC_RESET_CAUSE (Register R16): Reset Cause
     171Supported on '''GSCv3 firmware v53+''', the GSC_RESET_CAUSE register describes the event that caused the boards power supply to be reset by the GSC. This register is read by up to date Newport and Venice boot firmware and displays an ASCII flag representation. See the [#reset-cause reset cause] section for more detail.
     172
     173||= Value =||= Name =||= ASCII Flag =||= Description =||
     174|| 0  || RST_CAUSE_VIN             || VIN || Board power was cycled externally; no reset ||
     175|| 1  || RST_CAUSE_PB              || PB || User pushbutton ||
     176|| 2  || Reserved                  || - || - ||
     177|| 3  || RST_CAUSE_CPU             || CPU || CPU watchdog ||
     178|| 4  || RST_CAUSE_TEMP_LOCAL      || TEMP_L || Board Temperature exceeded spec ||
     179|| 5  || RST_CAUSE_TEMP_REMOTE     || TEMP_R || CPU Temperature exceeded spec ||
     180|| 6  || RST_CAUSE_SLEEP           || SLEEP || GSC woke board from sleep ||
     181|| 7  || RST_CAUSE_BOOT_WDT        || BOOT_WDT1 || Boot watchdog ||
     182|| 8  || RST_CAUSE_BOOT_WDT_MANUAL || BOOT_WDT2 || User pushbutton 5x to toggle boot device ||
     183|| 9  || RST_CAUSE_SOFT_PWR        || SOFT_PWR || Button press from soft power control ||
     184
     185
     186[=#GSC_INTERRUPT_SOURCE_1]
     187=== GSC_INTERRUPT_SOURCE_1 (Register R17): Interrupt Source 1
     188
     189||= Value =||= Name =||= Description =||
     190|| 0 || GSP_IRQ_OVRTMP_LOCAL || When set the local temp rose above CRIT_BOARD_TEMP ||
     191|| 1 || GSP_IRQ_OVRTMP_REMOTE || When set the remote temp sensor asserted its ALERTJ signal ||
     192
     193[=#GSC_INTERRUPT_ENABLE_1]
     194=== GSC_INTERRUPT_ENABLE_1 (Register R18): Interrupt Enable 1
     195
     196||= Value =||= Name =||= Description =||
     197|| 0 || GSP_IRQ_OVRTMP_LOCAL || Set to enable the local temp rose above CRIT_BOARD_TEMP interrupt ||
     198|| 1 || GSP_IRQ_OVRTMP_REMOTE || Set to enable the remote temp sensor asserted ALERTJ signal interrupt ||
     199
     200[=#gsc_thermal_protect]
     201=== GSC_THERMAL_PROTECT (Register R19): Thermal Protection Configuration
     202Supported on '''GSCv3 firmware v53+''', the GSC_THERMAL_PROTECT register configures the thermal protection feature.
     203
     204||= Bit =||= Name =||= Description =||
     205|| 0     || GSC_TP_ENABLE || 1 = Enable Thermal protection ||                                     
     206
     207[=#GSC_BOOT_OPTIONS]
     208=== GSC_BOOT_OPTIONS (Register R21): Boot Control Options
     209
     210||= Value =||= Name =||= Description =||
     211|| 0 || GSC_SWITCH_BOOT_SELECT || Boot device select. Clear for primary, set for alt device. This bit is also controlled by the [#UserPushbutton user pushbutton] 5x press behavior.  ||
     212
     213[=#GSC_MEM_ACCESS_PAGE]
     214=== GSC_MEM_ACCESS_PAGE (Register R22): Direct Memory Access Page Number
     215
     216||= Value =||= Name =||= Description =||
     217|| 0-7 || GSC_PAGE_NUMBER || Page address offset when direct reading the GSC flash ||
     218
     219This API which is implemented over I2C on address {{{0x5f}}} allows a user to do direct memory reads over the entirety of the accessible memory range ({{{0x0000-0xFFFF}}}). It is used by constructing a 16 bit address with the top byte (a.k.a. page) being set by writing to an undocumented register at address {{{0x20}}} offset {{{0x1f}}}. The bottom byte is then added on via standard I2C protocol. Memory writes are not supported with this API. In order to simplify the usage of this API, a bash script was created that will be posted on the wiki and/or given to FAE's to distribute as they see fit. The name of the script is {{{gsc_direct_mem.sh}}} and the contents are included below.
     220
     221 [[CollapsibleStart(GSC Direct Memory Read Script)]]
     222{{{#!bash
     223#!/bin/bash
     224
     225[ "$#" -ne 2 ] && {
     226        echo "This script acts as a wrapper around I2C commands in order to do direct memory reads of the GSC."
     227        echo "It will output the i2c response in an i2cdump type format."
     228        echo
     229        echo "Usage: $0 <offset> <length>"
     230        echo
     231        echo "Example usage to read all 2000(0x7d0) peripheral register values:"
     232        echo "  $0 0x100 0x7d0"
     233        exit 1
     234}
     235
     236# Store inputs
     237BUS=0
     238ADDR=0x5e
     239OFFSET=$1
     240LENGTH=$2
     241
     242# Misc variables
     243COUNT=0
     244PAGE=0
     245PRINTVAL=0x0000
     246REMAINDER=0
     247HIGH=
     248RETURN=
     249
     250# Calculate initial page number based on passed in offset
     251PAGE=$((OFFSET / 0x100))
     252OFFSET=$((OFFSET % 0x100))
     253
     254echo "      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f     0123456789abcdef"
     255while [[ $COUNT -ne $LENGTH ]]; do
     256        # Set the page number accordingly
     257        i2cset -f -y 0 0x20 0x16 $PAGE
     258
     259        # Do either a full i2cdump or specify a range if bytes aren't a 0x100 aligned block
     260        if [[ $(($LENGTH - $COUNT)) -lt 0x100 || $OFFSET -ne 0 ]]; then
     261                HIGH=$(($LENGTH - $COUNT - 1 + $OFFSET))
     262                # Record remainder for i2c 0x100 upper range limit
     263                if [[ $HIGH -gt 0x100 ]]; then
     264                        REMAINDER=$(($HIGH + 1 - 0x100))
     265                else
     266                        REMAINDER=0
     267                fi
     268
     269                RETURN=$(i2cdump -f -y -r ${OFFSET}-$(($HIGH - $REMAINDER)) 0 $ADDR b | grep ':')
     270                COUNT=$(($HIGH - $REMAINDER - $OFFSET + 1 + $COUNT))
     271                OFFSET=0
     272        else
     273                RETURN=$(i2cdump -f -y 0 $ADDR b | grep ':')
     274                COUNT=$(($COUNT + 0x100))
     275        fi
     276
     277        if [[ "$RETURN" ]]; then # Only print reads
     278                # Format output to be continuous and account for page increase
     279                echo "$RETURN" | while read x; do
     280                        printf "%04x" "$((0x$(echo $x | cut -d':' -f1) + $((PAGE * 0x100))))"
     281                        echo ":${x##*:}"
     282                done
     283        fi
     284
     285        # Increase the page count
     286        ((++PAGE))
     287done
     288}}}
     289[[CollapsibleEnd]]
     290
     291[=#GSC_CTRL_2]
     292=== GSC_CTRL_2 (Register R23): Pushbutton, Miscellaneous Configuration
     293Supported in '''GSCv3 firmware v58+'''.
     294
     295||= Value =||= Name =||= Description =||
     296|| 0 || GSC_10X_PRESS_DISABLE || Disable 10x press for loading FACTORY registers (see [#GSC_REGISTER_BACKUP register backup]) ||
     297|| 1 || GSC_SOFT_WAKE_PROTECT || Disable waking from soft power press if VIN below board preset minimum ||
     298
     299[=#GSC_SOFT_POWER_TIME]
     300=== GSC_SOFT_POWER_TIME (Register R26): Soft Power Press Time
     301Supported in '''GSCv3 firmware v58+'''. This register controls how long (in seconds) the pushbutton must be depressed before the board turns on/off via soft power control. The register is composed of an upper and lower nibble that control the minimum power on and power off press times respectively. The register defaults to a power on press time of {{{0}}} seconds and a power off press time of {{{1}}} second ({{{0x01}}}).
     302
     303||= Value =||= Name =||= Description =||
     304|| 0-3 || GSC_SOFT_POWER_TIME_ON || Minimum pushbutton press time required to wake, in seconds ||
     305|| 4-7 || GSC_SOFT_POWER_TIME_OFF || Minimum pushbutton press time required to sleep, in seconds ||
     306
     307[=#GSC_REGISTER_BACKUP]
     308=== GSC_REGISTER_BACKUP (Register R31): Register Backup Control
     309This register has an upper nibble password of value {{{0xA0}}} that should be bitwise OR'd with an enumerated value in the lower nibble that will be interpreted as the command. This register will self clear when the operation has completed. See the below [#reg_save_load Register Save/Load] section for more information.
     310
     311||= Value =||= Name =||= Description =||
     312|| 1 || GSC_REG_BKP_SAVE || Save current register values to USER backup area ||
     313|| 2 || GSC_REG_BKP_USER_LOAD || Load register values from USER backup ||
     314|| 3 || GSC_REG_BKP_FACTORY_LOAD || Load register values from FACTORY backup ||
     315|| 4-7 || GSC_REG_BKP_PASSWORD || Password for upper nibble ({{{0xA0}}}). Bitwise OR this value with lower nibble enumerated values described above ||
    58316
    59317
     
    8471105== Hardware Boot Watchdog ==
    8481106Gateworks boards benefit from a GSC Boot Watchdog which will cause a primary board power supply reset if the bootloader fails to load and disable it within {{{30}}} seconds. This protects against occasional chip errata that our hardware has no control over.
    849 
    850 
    851 [=#registers]
    852 == GSC Registers
    853 The System Specialized Functions described above are configured via a set of GSC registers in an i2c slave device at the 7-bit address of {{{0x20}}}.
    854 
    855 GSC Registers:
    856 ||= Reg Number =||= Reg Name           =||= Description                                 =||= Supported =||
    857 || 0            || GSC_CTRL_0           || Pushbutton Switch, CRC, Tamper Switch         || All ||
    858 || 1            || GSC_CTRL_1           || Sleep / Wakeup Control, Alternate Boot Device || All ||
    859 || 2-5          || GSC_SLEEP_WAKE_TIME  || Sleep Wakeup Timer                            || All ||
    860 || 6-9          || GSC_SLEEP_ADD        || Sleep Wakeup Additive Timer                   || All ||
    861 || 10           || GSC_INTERRUPT_SOURCE || Interrupt Source                              || All ||
    862 || 11           || GSC_INTERRUPT_ENABLE || Interrupt Enable                              || All ||
    863 || 12-13        || GSC_FIRMWARE_CRC     || Firmware CRC Value                            || All ||
    864 || 14           || GSC_FIRMWARE_VER     || Firmware Version                              || All ||
    865 || 15           || GSC_WRITE_PROTECT    || Write Protection                              || All ||
    866 || 16           || GSC_RESET_CAUSE      || Reset Cause                                   || GSCv3 ||
    867 || 17           || GSC_INTERRUPT_SOURCE_1 || Interrupt Source 1                          || GSCv3 ||
    868 || 18           || GSC_INTERRUPT_ENABLE_1 || Interrupt Enable 1                          || GSCv3 ||
    869 || 19           || GSC_THERMAL_PROTECT  || Thermal Protection                            || GSCv3 ||
    870 || 20           || GSC_CPU_SPEED_CTRL   || CPU Speed Control                             || GSCv3 ||
    871 || 21           || GSC_BOOT_OPTIONS     || Boot Control Options                          || GSCv3 ||
    872 || 22           || GSC_MEM_ACCESS_PAGE  || Direct Memory Access Page Number              || GSCv3 ||
    873 || 23           || GSC_CTRL_2           || Pushbutton Switch, Misc.                      || GSCv3 ||
    874 || 31           || GSC_REGISTER_BACKUP  || Thermal Protection                            || GSCv3 ||
    875 
    876 [=#gsc_ctrl_0]
    877 === GSC_CTRL_0 (Register R0): Pushbutton Switch, CRC, and Tamper Switch configuration
    878 ||= Bit =||= Name              =||= Description =||=Newport Defaults=||=Ventana Defaults||
    879 || 0     || PB_HARD_RESET       || 0 = Pushbutton Software Interrupt[[BR]] Generates GSC Interrupt (see R10.0/R11.0)[[BR]] 1 = Push button generates hard system reset to board when the button is[[BR]] activated and de-activated within 700ms ||Enabled||Enabled||
    880 || 1     || PB_CLEAR_SECURE_KEY || 0 = Clear '''Secure Key''' EEPROM disabled[[BR]] 1 = Clear GSC EEPROM user space when switch is activated three times with[[BR]] less than 700ms delay between each activation[[BR]] Generates GSC Intterupt ||Disabled||Disabled||
    881 || 2     || PB_SOFT_POWER_DOWN  || 0 = Soft Power Down disabled[[BR]] 1 = Soft Power Down enabled[[BR]]Hold down >1s to power down[[BR]]When powered down a momentary press will power up[[BR]] Generates push button interrupt ||Disabled||Disabled||
    882 || 3     || PB_BOOT_ALTERNATE   || 0 = Boot Alternate Device disabled.[[BR]] 1 = Boot Alternate Device Enabled[[BR]] The board will reset and boot from the Alternate Boot Device when the[[BR]] pushbutton is activated (quick press-and-release) 5 times in quick succession) ||Enabled||Disabled||
    883 || 4     || PERFORM_CRC         || 1 = Run CRC on GSC and store results in GSC_FIRMWARE_CRC (R12,R13)[[BR]] resets to 0 on completion of CRC ||Disabled||Disabled||
    884 || 5     || TAMPER_DETECT       || 0 = Do not activate tamper switch operation[[BR]] 1 = Activate tamper switch operation. When Activated, if the tamper switch[[BR]] is released, the contents in the EEPROM user space will be erased[[BR]] Generates tamper switch interrupt. ||Disabled||Disabled||
    885 || 6     || SWITCH_HOLD         || 0 = Switch hold disabled.[[BR]] 1 = Switch Hold On. When the switch is held down for >700ms an interrupt[[BR]] will be generated. See interrupt Enable / Status registers. (supported in rev29+) ||Disabled||Disabled||
    886 || 7     || CPU_WDOG_POWERCYCLE || 0 = Disabled. CPU WDOG signals only trigger a software reset. [[BR]] 1 = Enabled. Convert CPU WDOG signal into a full board power cycle. (GSCv3 only) || Enabled || Not supported ||
    887 
    888 [=#gsc_ctrl_1]
    889 === GSC_CTRL_1 (Register R1): Sleep Wakeup Timer Control
    890 ||= Bit =||= Name              =||= Description =||
    891 || 0     || SLEEP_ENABLE        || 0 = Disable hardware sleep operation[[BR]] 1 = Enable hardware sleep operation ||
    892 || 1     || ACTIVATE_SLEEP      || 0 = Do not activate hardware sleep operation[[BR]] 1 = Activate hardware sleep operation (see GSC_SLEEP_WAKE) ||
    893 || 2     || LATCH_SLEEP_ADD     || 0 = Reserved[[BR]] 1 = Latch and add GSC_SLEEP_ADD registers to GSC_SLEEP_WAKE[[BR]]Resets to Zero on Completion ||
    894 || 3     || SLEEP_NOWAKEPB      || 0 = Wake from sleep on pushbutton 1 = do not wake on sleep until sleep wakeup time ||
    895 || 4     || RESERVED            || ||
    896 || 5     || RESERVED            || ||
    897 || 6     || SWITCH_BOOT_ENABLE  || 0 = Auto Switch boot disabled[[BR]] 1 = Auto Switch boot enabled[[BR]]Note this is set and used at powerup by the GSC as a '''boot watchdog''' on Ventana boards ||
    898 || 7     || SWITCH_BOOT_CLEAR   || Auto Switch boot clear[[BR]]Set to disable auto switch boot countdown timer[[BR]]Note this is set and used at bootup by the bootloader as a '''boot watchdog''' on Ventana boards ||
    899 
    900 [=#gsc_sleep_wake_time]
    901 === GSC_SLEEP_WAKE_TIME (Registers R2-R5): Sleep Wakeup Time
    902 ||= Bit =||= Description =||
    903 || 0-31  || RTC Value to wake the board when in sleep[[BR]] (least significant byte first) ||
    904 
    905 [=#gsc_sleep_add]
    906 === GSC_SLEEP_ADD (Registers R6-R9): Sleep Wakeup Time Additive
    907 ||= Bit =||= Description =||
    908 || 0-31  || Add to current RTC and store in GSC_SLEEP_WAKE_TIME[[BR]] latched with R1.2[[BR]] (least significant byte first) ||
    909 
    910 [=#gsc_interrupt_status]
    911 === GSC_INTERRUPT_STATUS (Register R10): Interrupt Source
    912 The GSC includes a single active-low level-triggered interrupt connected to an interrupt input on the ARM host processor. The GSC includes several possible interrupt sources with a control register to enable the desired interrupts and a status register to determine which are active. The following bits will indicate the cause of the host interrupt assertion which will remain asserted until all enabled bits are clear.
    913 
    914 ||= Bit =||= Name =||= Description =||
    915 || 0     || IRQ_PB            || When set a pushbutton switch interrupt has occurred ||
    916 || 1     || IRQ_KEY_ERASED    || When set a '''Secure Key''' erase operation has completed ||
    917 || 2     || IRQ_EEPROM_WP     || When set an EEPROM WP violation occurred[[BR]] (write to EEPROM while GSC_EEPROM_WP_ALL or GSC_EEPROM_WP_BOARDINFO was enabled) ||
    918 || 3     ||                   || Reserved ||
    919 || 4     || IRQ_GPIO_CHANGE   || When set a GPIO interrupt has occurred ||
    920 || 5     || IRQ_TAMPER_DETECT || When set a tamper switch interrupt has occurred ||
    921 || 6     || IRQ_WDOG_TIMEOUT  || When set a boot watchdog timeout has occurred resulting in the board being reset ||
    922 || 7     || IRQ_SWITCH_HOLD   || When set a 'switch hold' interrupt has occurred ||
    923 
    924 For more information see [#gsc-interrupts gsc-interrupts]
    925 
    926 [=#gsc_interrupt_enable]
    927 === GSC_INTERRUPT_ENABLE (Register R11): Interrupt Enable (refer to bits above)
    928 ||= Bit =||= Name =||= Description =||
    929 || 0     || IRQ_PB                || Set to enable pushbutton switch interrupt ||
    930 || 1     || IRQ_SECURE_KEY_ERASED || Set to enable '''Secure Key''' erase operation interrupt ||
    931 || 2     || IRQ_EEPROM_WP         || Set to enable EEPROM WP violation interrupt ||
    932 || 3     ||                       || Reserved ||
    933 || 4     || IRQ_GPIO_CHANGE       || Set to enable GPIO interrupt ||
    934 || 5     || IRQ_TAMPER_DETECT     || Set to enable Tamper detect interrupt ||
    935 || 6     || IRQ_WDOG_TIMEOUT      || Set to enable Boot Watchdog timeout interrupt ||
    936 || 7     || IRQ_SWITCH_HOLD       || Set to enable pushbutton switch 'hold' interrupt ||
    937 
    938 For more information see [#gsc-interrupts gsc-interrupts]
    939 
    940 [=#gsc_firmware_crc]
    941 === GSC_FIRMWARE_CRC (Register R12,R13): GSC Firmware CRC Value
    942 ||= Bit  =||= Description =||
    943 ||  0-15  || Contains the 16-bit cyclic redundancy check value for the GSP Flash memory (least significant byte first)[[BR]] The GSC performs a CRC check when R0.4 is set[[BR]] Once R0.4 is clear, R12 and R13 (16-bit lsb) contain an accurate CRC. ||
    944 
    945 
    946 [=#gsc_firmware_ver]
    947 === GSC_FIRMWARE_VER (Register R14): GSC Firmware Version
    948 ||= Bit =||= Description                            =||
    949 || 0-7   || Contains the GSC firmware version number ||
    950 
    951 
    952 [=#gsc_write_protect]
    953 === GSC_WRITE_PROTECT (Register R15): Write Protection
    954 ||= Bit =||= Name =||= Description =||
    955 || 0     || GSC_EEPROM_WP_ALL || 1 = Write Protect all EEPROM regions ||
    956 || 1     || GSC_EEPROM_WP_BOARDINFO || 1 = Write Protect the reserved Gateworks '''Board Info''' EEPROM section          ||
    957 || 2     || Reserved || - ||
    958 || 3-7   || GSC_WP_PASSWD || Must be 0xB when altering bits[0:2] (ie write 0x59 (0xB<<3|0x1) to enable WP_ALL) ||
    959 
    960 [=#gsc_reset_cause]
    961 === GSC_RESET_CAUSE (Register R16): Reset Cause
    962 Supported on '''GSCv3 firmware v53+''', the GSC_RESET_CAUSE register describes the event that caused the boards power supply to be reset by the GSC. This register is read by up to date Newport and Venice boot firmware and displays an ASCII flag representation. See the [#reset-cause reset cause] section for more detail.
    963 
    964 ||= Value =||= Name =||= ASCII Flag =||= Description =||
    965 || 0  || RST_CAUSE_VIN             || VIN || Board power was cycled externally; no reset ||
    966 || 1  || RST_CAUSE_PB              || PB || User pushbutton ||
    967 || 2  || Reserved                  || - || - ||
    968 || 3  || RST_CAUSE_CPU             || CPU || CPU watchdog ||
    969 || 4  || RST_CAUSE_TEMP_LOCAL      || TEMP_L || Board Temperature exceeded spec ||
    970 || 5  || RST_CAUSE_TEMP_REMOTE     || TEMP_R || CPU Temperature exceeded spec ||
    971 || 6  || RST_CAUSE_SLEEP           || SLEEP || GSC woke board from sleep ||
    972 || 7  || RST_CAUSE_BOOT_WDT        || BOOT_WDT1 || Boot watchdog ||
    973 || 8  || RST_CAUSE_BOOT_WDT_MANUAL || BOOT_WDT2 || User pushbutton 5x to toggle boot device ||
    974 || 9  || RST_CAUSE_SOFT_PWR        || SOFT_PWR || Button press from soft power control ||
    975 
    976 
    977 [=#GSC_INTERRUPT_SOURCE_1]
    978 === GSC_INTERRUPT_SOURCE_1 (Register R17): Interrupt Source 1
    979 
    980 ||= Value =||= Name =||= Description =||
    981 || 0 || GSP_IRQ_OVRTMP_LOCAL || When set the local temp rose above CRIT_BOARD_TEMP ||
    982 || 1 || GSP_IRQ_OVRTMP_REMOTE || When set the remote temp sensor asserted its ALERTJ signal ||
    983 
    984 [=#GSC_INTERRUPT_ENABLE_1]
    985 === GSC_INTERRUPT_ENABLE_1 (Register R18): Interrupt Enable 1
    986 
    987 ||= Value =||= Name =||= Description =||
    988 || 0 || GSP_IRQ_OVRTMP_LOCAL || Set to enable the local temp rose above CRIT_BOARD_TEMP interrupt ||
    989 || 1 || GSP_IRQ_OVRTMP_REMOTE || Set to enable the remote temp sensor asserted ALERTJ signal interrupt ||
    990 
    991 [=#gsc_thermal_protect]
    992 === GSC_THERMAL_PROTECT (Register R19): Thermal Protection Configuration
    993 Supported on '''GSCv3 firmware v53+''', the GSC_THERMAL_PROTECT register configures the thermal protection feature.
    994 
    995 ||= Bit =||= Name =||= Description =||
    996 || 0     || GSC_TP_ENABLE || 1 = Enable Thermal protection ||                                     
    997 
    998 [=#GSC_BOOT_OPTIONS]
    999 === GSC_BOOT_OPTIONS (Register R21): Boot Control Options
    1000 
    1001 ||= Value =||= Name =||= Description =||
    1002 || 0 || GSC_SWITCH_BOOT_SELECT || Boot device select. Clear for primary, set for alt device. This bit is also controlled by the [#UserPushbutton user pushbutton] 5x press behavior.  ||
    1003 
    1004 [=#GSC_MEM_ACCESS_PAGE]
    1005 === GSC_MEM_ACCESS_PAGE (Register R22): Direct Memory Access Page Number
    1006 
    1007 ||= Value =||= Name =||= Description =||
    1008 || 0-7 || GSC_PAGE_NUMBER || Page address offset when direct reading the GSC flash ||
    1009 
    1010 This API which is implemented over I2C on address {{{0x5f}}} allows a user to do direct memory reads over the entirety of the accessible memory range ({{{0x0000-0xFFFF}}}). It is used by constructing a 16 bit address with the top byte (a.k.a. page) being set by writing to an undocumented register at address {{{0x20}}} offset {{{0x1f}}}. The bottom byte is then added on via standard I2C protocol. Memory writes are not supported with this API. In order to simplify the usage of this API, a bash script was created that will be posted on the wiki and/or given to FAE's to distribute as they see fit. The name of the script is {{{gsc_direct_mem.sh}}} and the contents are included below.
    1011 
    1012  [[CollapsibleStart(GSC Direct Memory Read Script)]]
    1013 {{{#!bash
    1014 #!/bin/bash
    1015 
    1016 [ "$#" -ne 2 ] && {
    1017         echo "This script acts as a wrapper around I2C commands in order to do direct memory reads of the GSC."
    1018         echo "It will output the i2c response in an i2cdump type format."
    1019         echo
    1020         echo "Usage: $0 <offset> <length>"
    1021         echo
    1022         echo "Example usage to read all 2000(0x7d0) peripheral register values:"
    1023         echo "  $0 0x100 0x7d0"
    1024         exit 1
    1025 }
    1026 
    1027 # Store inputs
    1028 BUS=0
    1029 ADDR=0x5e
    1030 OFFSET=$1
    1031 LENGTH=$2
    1032 
    1033 # Misc variables
    1034 COUNT=0
    1035 PAGE=0
    1036 PRINTVAL=0x0000
    1037 REMAINDER=0
    1038 HIGH=
    1039 RETURN=
    1040 
    1041 # Calculate initial page number based on passed in offset
    1042 PAGE=$((OFFSET / 0x100))
    1043 OFFSET=$((OFFSET % 0x100))
    1044 
    1045 echo "      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f     0123456789abcdef"
    1046 while [[ $COUNT -ne $LENGTH ]]; do
    1047         # Set the page number accordingly
    1048         i2cset -f -y 0 0x20 0x16 $PAGE
    1049 
    1050         # Do either a full i2cdump or specify a range if bytes aren't a 0x100 aligned block
    1051         if [[ $(($LENGTH - $COUNT)) -lt 0x100 || $OFFSET -ne 0 ]]; then
    1052                 HIGH=$(($LENGTH - $COUNT - 1 + $OFFSET))
    1053                 # Record remainder for i2c 0x100 upper range limit
    1054                 if [[ $HIGH -gt 0x100 ]]; then
    1055                         REMAINDER=$(($HIGH + 1 - 0x100))
    1056                 else
    1057                         REMAINDER=0
    1058                 fi
    1059 
    1060                 RETURN=$(i2cdump -f -y -r ${OFFSET}-$(($HIGH - $REMAINDER)) 0 $ADDR b | grep ':')
    1061                 COUNT=$(($HIGH - $REMAINDER - $OFFSET + 1 + $COUNT))
    1062                 OFFSET=0
    1063         else
    1064                 RETURN=$(i2cdump -f -y 0 $ADDR b | grep ':')
    1065                 COUNT=$(($COUNT + 0x100))
    1066         fi
    1067 
    1068         if [[ "$RETURN" ]]; then # Only print reads
    1069                 # Format output to be continuous and account for page increase
    1070                 echo "$RETURN" | while read x; do
    1071                         printf "%04x" "$((0x$(echo $x | cut -d':' -f1) + $((PAGE * 0x100))))"
    1072                         echo ":${x##*:}"
    1073                 done
    1074         fi
    1075 
    1076         # Increase the page count
    1077         ((++PAGE))
    1078 done
    1079 }}}
    1080 [[CollapsibleEnd]]
    1081 
    1082 [=#GSC_CTRL_2]
    1083 === GSC_CTRL_2 (Register R23): Pushbutton, Miscellaneous Configuration
    1084 Supported in '''GSCv3 firmware v58+'''.
    1085 
    1086 ||= Value =||= Name =||= Description =||
    1087 || 0 || GSC_10X_PRESS_DISABLE || Disable 10x press for loading FACTORY registers (see [#GSC_REGISTER_BACKUP register backup]) ||
    1088 || 1 || GSC_SOFT_WAKE_PROTECT || Disable waking from soft power press if VIN below board preset minimum ||
    1089 
    1090 [=#GSC_SOFT_POWER_TIME]
    1091 === GSC_SOFT_POWER_TIME (Register R26): Soft Power Press Time
    1092 Supported in '''GSCv3 firmware v58+'''. This register controls how long (in seconds) the pushbutton must be depressed before the board turns on/off via soft power control. The register is composed of an upper and lower nibble that control the minimum power on and power off press times respectively. The register defaults to a power on press time of {{{0}}} seconds and a power off press time of {{{1}}} second ({{{0x01}}}).
    1093 
    1094 ||= Value =||= Name =||= Description =||
    1095 || 0-3 || GSC_SOFT_POWER_TIME_ON || Minimum pushbutton press time required to wake, in seconds ||
    1096 || 4-7 || GSC_SOFT_POWER_TIME_OFF || Minimum pushbutton press time required to sleep, in seconds ||
    1097 
    1098 [=#GSC_REGISTER_BACKUP]
    1099 === GSC_REGISTER_BACKUP (Register R31): Register Backup Control
    1100 This register has an upper nibble password of value {{{0xA0}}} that should be bitwise OR'd with an enumerated value in the lower nibble that will be interpreted as the command. This register will self clear when the operation has completed. See the below [#reg_save_load Register Save/Load] section for more information.
    1101 
    1102 ||= Value =||= Name =||= Description =||
    1103 || 1 || GSC_REG_BKP_SAVE || Save current register values to USER backup area ||
    1104 || 2 || GSC_REG_BKP_USER_LOAD || Load register values from USER backup ||
    1105 || 3 || GSC_REG_BKP_FACTORY_LOAD || Load register values from FACTORY backup ||
    1106 || 4-7 || GSC_REG_BKP_PASSWORD || Password for upper nibble ({{{0xA0}}}). Bitwise OR this value with lower nibble enumerated values described above ||
    11071107
    11081108[=#reg_save_load]