Changes between Version 68 and Version 69 of gsc


Ignore:
Timestamp:
01/05/2021 04:48:30 PM (19 months ago)
Author:
Bobby Jones
Comment:

replace interrupt "_SOURCE*" mentions with "_STATUS" for consistency

Legend:

Unmodified
Added
Removed
Modified
  • gsc

    v68 v69  
    6868|| 2-5          || [#gsc_sleep_wake_time GSC_SLEEP_WAKE_TIME]  || Sleep Wakeup Timer                            || All ||
    6969|| 6-9          || [#gsc_sleep_add GSC_SLEEP_ADD]        || Sleep Wakeup Additive Timer                   || All ||
    70 || 10           || [#gsc_interrupt_status GSC_INTERRUPT_SOURCE_0] || Interrupt Source                              || All ||
     70|| 10           || [#gsc_interrupt_status GSC_INTERRUPT_STATUS_0] || Interrupt Source                              || All ||
    7171|| 11           || [#gsc_interrupt_enable GSC_INTERRUPT_ENABLE_0] || Interrupt Enable                              || All ||
    7272|| 12-13        || [#gsc_firmware_crc GSC_FIRMWARE_CRC]     || Firmware CRC Value                            || All ||
     
    7474|| 15           || [#gsc_write_protect GSC_WRITE_PROTECT]    || Write Protection                              || All ||
    7575|| 16           || [#gsc_reset_cause GSC_RESET_CAUSE]      || Reset Cause                                   || GSCv3 ||
    76 || 17           || [#GSC_INTERRUPT_SOURCE_1 GSC_INTERRUPT_SOURCE_1] || Interrupt Source 1                          || GSCv3 ||
     76|| 17           || [#GSC_INTERRUPT_STATUS_1 GSC_INTERRUPT_STATUS_1] || Interrupt Source 1                          || GSCv3 ||
    7777|| 18           || [#GSC_INTERRUPT_ENABLE_1 GSC_INTERRUPT_ENABLE_1] || Interrupt Enable 1                          || GSCv3 ||
    7878|| 19           || [#gsc_thermal_protect GSC_THERMAL_PROTECT]  || Thermal Protection                            || GSCv3 ||
     
    184184
    185185
    186 [=#GSC_INTERRUPT_SOURCE_1]
    187 === GSC_INTERRUPT_SOURCE_1 (Register R17): Interrupt Source 1
     186[=#GSC_INTERRUPT_STATUS_1]
     187=== GSC_INTERRUPT_STATUS_1 (Register R17): Interrupt Source 1
    188188
    189189||= Value =||= Name =||= Description =||
     
    967967The Gateworks System Controller has an interrupt signal to the host processor which it asserts when an event has occurred worth notifying the host about. The [#gsc_interrupt_enable GSC_INTERRUPT_ENABLE_0 (R11)] register defines what events can trigger an interrupt and an interrupt service routine can query the [#gsc_interrupt_status GSC_INTERRUPT_STATUS_0 (R10)] register to see what events are present. The interrupt remains asserted until all status bits are cleared by writing 0's to those bits in the [#gsc_interrupt_status GSC_INTERRUPT_STATUS_0 (R10)] register.
    968968
    969 '''GSCv3''' has an additional pair of interrupt registers represented by [#GSC_INTERRUPT_SOURCE_1 GSC_INTERRUPT_STATUS_1 (R17)] and [#GSC_INTERRUPT_ENABLE_1 GSC_INTERRUPT_ENABLE_1 (R18)].
     969'''GSCv3''' has an additional pair of interrupt registers represented by [#GSC_INTERRUPT_STATUS_1 GSC_INTERRUPT_STATUS_1 (R17)] and [#GSC_INTERRUPT_ENABLE_1 GSC_INTERRUPT_ENABLE_1 (R18)].
    970970
    971971[=#IRQ_PB]
     
    12411241  - Add Venice rev B ADC rails
    12421242  - Fix irq deassertion on over temp event
    1243   - Prevent external setting of GSC_INTERRUPT_SOURCE_* bits
     1243  - Prevent external setting of GSC_INTERRUPT_STATUS_* bits
    12441244 * v57: 20200716
    12451245  - Fix issues related to updating with gsc_update